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Features
* AVR(R) Microcontroller * Clock Generator Provides CPU Rates up to 24 MHz * Programmable UART with 16-byte FIFOs at the Receiver Side (1), with a Maximum Rate * * * * * * * * * * * * * * *
of 921K Baud Programmable SPI Interface Full-speed USB Function Controller 2K Bytes of SRAM for Data, Stack and Program Variables 2K Bytes of Dual-port RAM, Shared among the USB, UART and AVR 8K x 16-bit SRAM for Program Execution Internal ROM for the Bootstrap Loader One USB Control Endpoint Six USB Programmable Endpoints (up to 64 Bytes) with Double-buffered FIFOs for Back-to-back Transfers One 8-bit Timer/Counter One 16-bit Timer/Counter External and Internal Interrupt Sources Programmable Watchdog Timer Independent UART BRG Oscillator 64-lead TQFP Package and BGA Package 3.3V Operation
AVR(R)-based Bridge between Full-speed USB and Fast Serial Asynchronous Interfaces AT76C711
Pin Configuration (TQFP)
NC VCC GND PD7_INT1 PD6_INT0 PD5 PD4 PD3 PD2 PD1_SOUT PD0_SIN UXTAL0 UXTAL1 GND LFTU VCC TCK TP LC VCC GND DP DM SUSP GND VCC PM0 PM1 PC0 PC1 PC2 PC3 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 RST PB0_T0 PB1_T1 PB2_ICP PB3 PB4_SS PB5_MOSI PB6_MISO PB7_SCK VCC LFT GND XTAL1 XTAL2 TEST1 PSDIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 P_RX P_TX GND VCC PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 VCC GND TEST2 ECK
Rev. 1643C-USB-10/02
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Description
The Atmel AT76C711 is a compound USB device designed to provide a high-speed USB interface to devices that need to communicate with a host through fast serial links, like UARTs and IrDA interfaces. It is based on the AVR-enhanced RISC architecture and consists of a USB function interface with a devoted DMA controller for fast data transfers between the buffers of the USB endpoints and a shared DPRAM of 2K bytes, 2K bytes SRAM for data, stack and program variables, a Synchronous Peripheral Interface (SPI), a UART supporting a maximum rate of 921K baud with DMA channels for data transfers to/from the DPRAM and an 8K x 16-bit SRAM for microcode execution. An IrDA controller is also provided, attached to a second UART module, and is able to communicate with an IrDA transceiver with a maximum rate of 1.2 Mbps. An internal ROM contains the bootstrap loader which reads the instructions from an external serial DataFlash(R) of Atmel AT45 Series and stores them into the on-chip program SRAM. Alternatively, microcode can be stored in the program SRAM using the slave program mode while the chip is in the reset state. The USB Hardware block consists of a USB transceiver, the SIE, endpoint controllers and an interface to the microcontroller. The USB Hardware interfaces to the USB host at the packet level. The microcontroller firmware handles the higher-level USB protocol layers that are not processed by the USB Hardware and in addition, it performs the peripheral control functions. The device is suitable for applications where minimization of power dissipation is required, since there are no power-consumable transactions with external parallel devices.
Block Diagram
Program Memory Controller Osc Clock Generator UART 1 Timers AVR Core SRAM WD IrDA 1.0 EncDec
USB
Address Decoder
SPI DPRAM DMA Controller UART0
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General-Purpose I/O
AT76C711
Applications
The AT76C711 can be used in applications where peripherals supporting fast serial asynchronous or synchronous transfer of data have to communicate with a host or other peripherals through a high-speed serial link, like USB. A typical application of AT76C711 and its functional diagram are shown in Figures 1 and 2. Typical areas of AT76C711 usage are: * * * * * * * Connection of Network Interface Cards (NICs) to a host system Wireless communications Bridging of microcontrollers with different types of serial interfaces USB to UART bridge USB to IrDA bridge IrDA to UART bridge Packet adaptation of network protocol packets to USB requirements
Figure 1. Typical AT76C711 Application
USB
AT76C 711 Desktop System
UART
Network Adaptor RF Trsc RF Trsc Network Adaptor Printer
Figure 2. Functional Diagram
S/U XTAL1 XTAL2 LFT
Debug ROM
16K x 16-bit SRAM
Clock Generator SRAM
IrDA 1.0 EncDec UART 1 Timers WD
Data
Program Bus AVR Core
SUSP
Interrupt Lines
DATA PORT REGISTERS - PORT DIRECTION REGISTERS DRIVERS/BUFFERS
PROGRAM MEMORY CONTROLLER
CLOCK Osc
PA0/SIN1/IrRx PA1/SOUT1/IrT PA2 PA3 PA4 PA5 PA6 PA7
2K x 8-bit
DP DM
USB
RAM Address Bus & Bi-directional Data Bus
TDMAC, RDMAC, UINT
PB0/T0 PB1/T1 PB2/INT0 PB3/INT1 PB4/SS PB5/MOSI PB6/MISO PB7/SCK PC0-3 PD0/SIN0 PD1/SOUT0 PD2/RTS0 PD3/CTS0 PD4/DSR0 PD5/DTR0 PD6 PD7 UXTALO UXTALI
Address & Control Bus for AVR Register File Programming RST
TXRDY RXRDY UINT
Address Decoder
/
SPI USART 0 UART Osc
DPRAM 2K x 8-bit
DMA Controller
USCLK
LFTU
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Pin Summary - Pin Assignment in Alphabetical Order
Type:
Pin # TQFP 23 22 33 19 14 50 * 64 48 47 37 38 39 40 41 42 43 Notes:
I = Input, O = Output, OD = Output, Open Drain, B = Bi-directional, V = Power Supply, Ground
Pin # BGA H4 H3 H8 F3 E2 A7 *** B2 B7 B8 E7 F8 E8 E5 D8 E6 D7 1. 2. 3. 4. Signal DM DP ECK LC LFT LFTU GND NC P_IRX P_ITX PA0 PA1 PA2 PA3 PA4 PA5 PA6 I O B B B B B B B Type B B I I I I V Pin # TQFP 44 2 3 4 5 6 7 8 9 29 30 31 32 54 55 56 57 Pin # BGA D6 B1 C3 C2 D2 C1 D1 D4 E1 H6 G6 H7 G7 A6 A5 D5 A4 Signal PA7 PB0_T0 PB1_T1 PB2_ICP PB3 PB4_SS PB5_MOSI PB6_MISO PB7_SCK PC0 PC1 PC2 PC3 PD0_SIN
PD1_SOUT
Type B B B B B B B B B B B B B B B B B
Pin # TQFP 58 59 60 61 16 1 27, 28 24 17 15 34 18 ** 51 52 11 12
Pin # BGA C5 B4 C4 A3 G2 A1 G5, F5 E4 H1 G1 G8 H2 **** B6 B5 F1 F2
Signal PD4 PD5 PD6_INT0 PD7_INT1 PSDIN RST PM0, PM1 SUSP TCK TEST1 TEST2 TP VCC UXTALI UXTALO XTAL1 XTAL2
Type B B B B I I I O I I I I V I O I O
PD2 PD3
(*) GND - TGFP: 12, 21, 25, 35, 46, 51, 62. (**) VCC - TQFP: 10, 20, 24, 36, 45, 49, 63. (***) GND - BGA: B3, C6, C7, E3, F6, H5, G4 (****) VCC - BGA: A2, A8, C8, F7, F4, G3, D3
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AT76C711
Pin Summary - Pin Assignment in Numerical Order
Pin # TQFP 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 Pin # BGA A1 B1 C3 C2 D2 C1 D1 D4 E1 D3 E2 E3 F1 F2 G1 G2 H1 H2 F3 G3 G4 H3 Signal RST PB0_T0 PB1_T1 PB2_ICP PB3 PB4_SS PB5_MOSI PB6_MISO PB7_SCK VCC LFT GND XTAL1 XTAL2 TEST1 PSDIN TCK TP LC VCC GND DP Type I B B B B B B B B V I V I O I I I I I V V B Pin # TQFP 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 Pin # BGA H4 E4 H5 F4 G5 F5 H6 G6 H7 G7 H8 G8 F6 F7 E7 F8 E8 E5 D8 E6 D7 D6 Signal DM SUSP GND VCC PM0 PM1 PC0 PC1 PC2 PC3 ECK TEST2 GND VCC PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 Type B O V V I I B B B B I I V V B B B B B B B B Pin # TQFP 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 Pin # BGA C8 C7 B8 B7 A8 A7 C6 B6 B5 A6 A5 D5 A4 C5 B4 C4 A3 B3 A2 B2 Signal VCC GND P_ITX P_IRX VCC LFTU GND UXTALI UXTALO PD0_SIN
PD1_SOUT
Type V V O I V I V I O B B B B B B B B V V V
PD2 PD3 PD4 PD5 PD6_INT0 PD7_INT1 GND VCC NC
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Signal Description (1)
Type:
Name
I = Input, O = Output, OD = Output, Open Drain, B = Bi-directional, V = Power Supply, Ground
Type Description
Program Memory Controller Signals PM0, PM1 PSDIN TP LC I I I I Configuration pins - See Figure 3 Program Serial Data-In: In slave program mode, this signal carries the serial program data that are samples with the positive edge of TCK. When RST is active (low), a high level of this signal, for at least two TCK pulses, forces the program address generator. Load Complete: A transition from low to high denotes the completion of program data transfer from the external device. The AVR will start executing instructions from the internal SRAM as soon as the RST goes high. A clock signal for sampling PSDIN input.
TCK Port Signals PA[0:7] PA[0:7]
I
B B
Port A, PA0 through PA7 - 8-bit bi-directional port. Port B, PB0 through PB7 - 8-bit bi-directional port. PB0, PB1, PB2, PB4 through PB7 are dualfunction as shown below: Port Alternate Function PB0 Timer/Counter0 clock input PB1 Timer/Counter1 clock input PB2 (ICP) Input Capture Pin for Timer/Counter1 PB4 (SS) SPI slave port select input PB5 (MOSI) SPI slave port select input PB6 (MISO) SPI master data-in, slave data-out PB7 (SCK) SPI master clock out, slave clock in Port C, PC0 through PC3 - 4-bit output port. Port D, PD0 through PD7 - 8-bit bi-directional I/O port. PD0, PD1 also serve as the data lines for the asynchronous serial port as listed below: Port Alternate Function PD0 (SIN) Serial Data-In (I): This pin provides the serial receive data input to 16550 UART. The SIN signal will be a logic "1" during reset, idle (no data). During the local loopback mode, the SIN input pin is disabled and SOUT data is internally connected to the UART SIN input. PD1 (SOUT) Serial Data Out (O): This pin provides the serial transmit data from the 16550 UART. The SOUT signal will be a logic "1" during reset, idle (no data). PD6 (INT0) External Interrupt0 source PD7 (INT1) External Interrupt1 source
PC[0:3] PD[0:7]
B B
USB Serial Interface B DP DM SUSP B O Upstream Plus USB I/O - DP and DM form the differential signal pin pair connected to the host controller or an upstream hub. Upstream Minus USB I/O Suspend: This output pin is deactivated (high) during normal operation. It is used to signal the host microcontroller that AT76C711 has received USB suspend signaling. This pin will stay asserted while AT76C711 is in the suspend mode. This pin is deactivated whenever a USB resume signaling is detected on DP and DM.
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Signal Description (Continued)(1)
Type:
Name Test Signals TEST1 TEST2 ECK IrDA Interface P_ITX O Infrared Data Out: This pin provides the serial transmit data from the IrDA codec to external IR Data Transceiver. This function is activated when the IrDA interface is enabled from PERIPHEN I/O Register. Infrared Data-In: This pin provides the serial receive data input from the external IR Data Transceiver to IrDA codec. This function is activated when the IrDA interface is enabled from PERIPHEN I/O Register. I I I Test signal for clocks (used in production phase only - normally tied to high) Test signal for monitoring internal signal levels using the four data ports (used in production phase only - normally tied to high) Clock pulse for activating various test modes when TEST2 is active
I = Input, O = Output, OD = Output, Open Drain, B = Bi-directional, V = Power Supply, Ground
Type Description
P_IRX
I
Other Signals GND VCC RST XTAL1 XTAL2 LFT UXTALI UXTALO LFTU Note: V V I I O I I O I Ground 3.3V power supply Reset: A low on this pin for two machine cycles, while the oscillator is running, resets the device. Oscillator Input: Input to the inverting oscillating amplifier. A 12 MHz clock oscillator should be applied. Oscillator Output: Output of the inverting oscillator amplifier. Master clock PLL LFT pin UART BRG Oscillator Input. Input to the UART oscillator amplifier. UART BRG Oscillator Output. Output of the UART oscillator amplifier. UART clock PLL LFT pin
1. Any signal with an OVERLINE indicates that it is an active low signal.
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Functional Description
Bootstrap ROM and Program Modes
The AT76C711 offers a variety of program modes that allow the user not only to upload the microcode to internal program SRAM but also to upgrade the system firmware that is contained in a serial AT45DB011 (or larger) Flash. AT76C711 supports one slave and three master program modes. The chip enters the slave program mode while in the reset state (RST active low) when it detects a positive edge transition of TP signal. The timing diagram of the procedure is depicted in Figure 3. Figure 3. Slave Program Mode Timing Diagram
RST TCK TP PSDIN LP
Slave Program Mode
Master Program Modes
On power-up or after a system reset, the bootstrap code traces the value of the PM0, PM1 signals and executes the respective task according to Figure 3. After the execution of any of the following tasks, the chip enters the normal mode and starts running the code loaded in the internal program SRAM.
PM0 1 0 0 PM1 x 0 1 Task SPI program mode: The internal program SRAM is loaded from the external serial Flash through the SPI. USB program mode: The host downloads the code to the internal program SRAM using the DFU protocol.(1) USB program mode with firmware upgrade: The host downloads pages of code to the internal program SRAM, which are then stored to the external SPI Flash.(1)
Note:
1. This mode is not supported in the current version of the chip.
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AT76C711
USB Hardware Block
USB Function Interface
The USB function interface consists of a Serial Interface Engine (SIE), a Serial Bus Controller (SBC) and a System Interface (SI). The SIE performs the clock/data separation, NRZI encoding and decoding, bit insertion and deletion, CRC generation and checking and the serial-parallel data conversion. The SBC consists of a protocol engine and a USB device with one control endpoint (EP0), four programmable endpoints, each with one 2 x 64-byte dedicated double-buffered FIFO and one programmable endpoint with one 2 x 16-byte double-buffered FIFO. Each EP can be programmed as isochronous, bulk or interrupt and can be configured either as IN or OUT. A pair endpoint address scheme is also supported for the first four programmable endpoints. According to this scheme, two endpoints may have the same address, provided one of them has been configured as IN and the other as OUT. The SBC manages the device address, monitors the status of the transactions, manages the FIFOs and communicates to the microcontroller through a set of status and control registers. The SI connects the SBC to the microcontroller and provides a DMA mechanism for transferring data between the DPRAM and the endpoint buffers. The function controller is implemented in the microcontroller's firmware. All interrupt signals from the USB functions are consolidated into a single interrupt line, which is input to the interrupt controller of the AVR. The following sections describe all the interrupt sources of the USB controller. All interrupts are masked through the interrupt enable registers that exist in the USB controller. The External Resume and Received Resume interrupts are cleared when the firmware clears the interrupt bit (the Suspend Interrupt is automatically cleared when activity is detected). All other interrupts are cleared when the processor sets a corresponding bit in an interrupt acknowledge register in the USB macro cell. There is only one bit for each interrupt source.
Interrupt Function EP0 Interrupt Function EP1 Interrupt Description See "Control Transfers at Function EP0" for details. For an OUT endpoint, it indicates that Function Endpoint1 has received a valid OUT packet and that the data is in the FIFO. For an IN endpoint, it means that the endpoint has received an IN token, sent out the data stored in the FIFO and received an ACK from the host. The FIFO is now ready to be written by new data from the processor. See Function EP1 Interrupt See Function EP1 Interrupt See Function EP1 Interrupt See Function EP1 Interrupt See Function EP1 Interrupt Whenever USB Hardware decodes a valid Start of Frame The USB Hardware has received a remote wake-up request. The USB Hardware has received resume signaling. The processor's firmware should take the function out of the suspended state. The USB Hardware has detected a suspend condition and is preparing to enter the suspend mode. The processor's firmware should place the embedded function in the suspend mode.
USB Function Controller USB Interrupt Handling
Function EP2 Interrupt Function EP3 Interrupt Function EP4 Interrupt Function EP5 Interrupt Function EP6 Interrupt SOF Received EXT RSM RCVD RSM SUSP
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Interrupt Priority
The USB macro interrupt priority is defined below.
Priority Level 2 (High level) 1: Same level (Low level) Interrupt Name SOF Received Function EP0 to EP6
Endpoint Interrupt
Endpoint interrupts are triggered by setting or clearing one or more bits in the Control and Status registers of an endpoint. These interrupts are caused by events during packet transactions and are different for control and non-control endpoints. The interrupts are described below, with respect to the Control and Status register bit definitions. Please refer to the "Endpoint Control and Status Register" definition on page 59.
Interrupt for Non-control Endpoints
1. RX OUT Packet 2. TX Packet Ready set clear (0 -> 1) (1 -> 0)
Interrupt for Control Endpoints
1. RX OUT Packet 2. RX SETUP 3. TX Packet Ready 4. TX Complete set set clear set (0 -> 1) (0 -> 1) (1 -> 0) (0 -> 1)
Serial Interface Engine
The SIE performs the following functions: * * * * * * * NRZI data encoding and decoding Bit stuffing and unstuffing CRC generation and checking ACKs and NACKs Identifying the type of a token Address checking Clock generation (via DPLL)
Function Interface Unit
The Function Interface Unit (FIU) provides the interface between the processor and the SIE. It manages transactions at the packet level with minimal intervention from the processor and contains the endpoints' buffers. The FIU is designed to operate in single-packet mode and to manage the USB packet protocol layer. To operate the FIU, the firmware must first enable the endpoints of the FIU, and select direction and ping-pong capability. After being enabled, the endpoints are in receive mode by default. The FIU notifies the processor when a valid token has been received. The data contained in the data packet will be supplied in the FIFO. The processor transfers the data to and from the host by interacting with each endpoint's FIFO and Control and Status registers. For example, when transmitting an IN packet, the FIU assembles the data of the endpoint's FIFO in a USB packet, transmits the packet and will signal the processor after the host receives and acknowledges the packet. The FIU performs automatic data packet retransmission and DATA0/DATA1 PID toggling. For SETUP tokens, the processor must parse the device request and then respond appropriately. After a SETUP token, there may be zero (0) or more DATA IN or DATA OUT packets for which the processor must either supply or receive the data.
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AT76C711
Control Transfers at Function EP0
Legend:
Host SETUP Stage 1. [SYNC]-[SETUP] 2. [SYNC]-[DATA0] 3. Data are put in FIFO 4. If CRC OK, Send [SYNC]-[ACK] 5. If CRC OK, Set RX_SETUP bit 6. INTERRUPT 7. Read UISR (bit 0 is set) 8. Read FCSR0 (RX_SETUP bit) 9. Read FBYTE_CNT0 10. Read FIFO0 11. Parse data If Set Control Direction Fill FIFO with data Set TX_Packet_Ready If Control Write Phase: Clear Control Direction If No Data Stage Phase: Clear Control Direction Set Data_End bit If Unsupported Command: Set FORCE_STALL bit 12. Clear RX_SETUP bit 13. SET UIAR (EP0 INTA) Status Stage, No DATA Stage 1. [SYNC]-[IN] 2. Send DATA1(0) 3. If CRC OK, Send [SYNC]-[ACK] 4. Set TX_Complete bit 5. INTERRUPT 6. Read UISR 7. Read CSR 8. If SET_ADDRESS, write to FADDR 9. Clear TX_Complete bit
DATA1/DATA0 DATA 1 (0)
= Data packet with DATA1 or DATA0 PID = Zero length DATA1 packet
USB Macro Microcontroller
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Control Transfers at Function EP0 (Continued)
Legend:
Host
DATA1/DATA0 DATA 1 (0)
= Data packet with DATA1 or DATA0 PID = Zero length DATA1 packet
USB Macro Microcontroller 10. Clear Data_End bit 11. Set FORCE_STALL bit 12. SET UIAR (EP0 INTA)
DATA Stage, Control READ 1. [SYNC]-[IN] 2. If TX_Packet_Ready = 1 Send DATA0/DATA1 else Send STALL 3. If CRC OK, Send [SYNC]-[ACK] 4. Clear TX_Packet_Ready 5. Set TX_Complete bit 6. INTERRUPT 7. Read UISR 8. Read CSR 9. Clear TX_Complete bit 10. If more data Fill FIFO with data Set TX_Packet_Ready else Set SET_FORCE_STALL 11. SET UIAR (EP0 INTA) STATUS/Early STATUS Stage with READ DATA Stage 1. [SYNC]-[OUT] 2. [SYNC]-[DATA1(0)] 3. If TX_Complete = 0 Send [SYNC]-[ACK] Set RX_OUT else Send [SYNC]-[NACK] 4. INTERRUPT 5. Read UISR 6. Read CSR 7. Clear RX_OUT 8. Set Data_End
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Control Transfers at Function EP0 (Continued)
Legend:
Host
DATA1/DATA0 DATA 1 (0)
= Data packet with DATA1 or DATA0 PID = Zero length DATA1 packet
USB Macro Microcontroller 9. Set FORCE_STALL COMMENT: A SETUP token will clear Data End. Not cleared by firware in case host retries 1 through 3. 10. SET UIAR (EP0 INTA)
DATA Stage, Control WRITE 1. [SYNC]-[OUT] 2. [SYNC]-[DATA1/DATA0] 3. Data are put in FIFO 4. If CRC OK, send [SYNC]-[ACK] 5. If CRC OK, set RX_OUT 6. INTERRUPT 7. Read UISR 8. Read CSR 9. Read FIFO 10. Clear RX_OUT If last packet, Set Data_End Set FORCE_STALL 11. SET UIAR (EP0 INTA) STATUS Stage with WRITE DATA Stage 1. [SYNC]-[IN] 2. Send DATA1(0) 3. If CRC OK, Send [SYNC]-[ACK] 4. Set TX_Complete bit 5. INTERRUPT 6. Read UISR 7. Read CSR 8. Clear TX_Complete bit 9. Clear Data_End bit 10. Set FORCE_STALL bit 11. SET UIAR (EP0 INTA)
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Interrupt and Bulk IN Transfers
1. The USB Hardware automatically starts the endpoint in receive mode and NAKs all IN tokens as long as bit CSR[TX Packet Ready] is cleared. 2. The processor checks bit CSR[TX Packet Ready]. If it is "0", writes the data into the FIFO, then sets CSR[TX Packet Ready]. 3. At the next IN token, the USB Hardware sends the packet out and waits for an ACK. Until an ACK is received, the USB Hardware will retransmit the packet. After receiving an ACK, the USB Hardware clears bit CSR[TX Packet Ready], signaling a successful completion to the processor. Figure 4. IN Token with and without Ping-pong
IN Token without Ping-pong
HOST Reads USB FIFO TX_Complete = 0 IN Token TX_pkt_rdy = 0 TX_Complete = 1 ACK Tx_pkt_rdy = 1 IN Token UC Fills USB FIFO HOST Reads USB FIFO TX_pkt_rdy = 0 TX_Complete = 1 ACK
IN Token with Ping-pong
UC Fills Data UC Pooling Tx_Complete Tx_pkt_rdy = 1 UC Fills Data UC Pooling Tx_Complete Tx_pkt_rdy = 1
HOST Reads Last Data TX_Complete = 0 IN Token TX_Complete = 1 ACK
HOST Reads Last Data TX_Complete = 0 IN Token TX_Complete = 1 ACK
Interrupt and Bulk OUT Transfers
The USB Hardware automatically starts the endpoint in receive mode. When an OUT token is received and if CSR[RX OUT Packet] is cleared, it stores the data in the FIFO. It ACKs the host if the data received are not corrupted, and then interrupts the processor. If CSR[RX OUT Packet] is set, the USB Hardware responds with a NAK to the incoming OUT token: The processor checks CSR[RX OUT Packet] and if it is "1", it reads the data from the FIFO and clears CSR[RX OUT Packet Ready]. Figure 5. OUT Token with and without Ping-pong
OUT Token without Ping-pong
HOST Fills USB FIFO UC Reads FIFO OUT Token OUT Token Rx_OUT = 1 ACK Rx_OUT = 0 OUT Token Rx_OUT = 1 HOST Fills USB FIFO UC Reads FIFO
OUT Token with Ping-pong
UC Reads Last Data Uc Pooling Rx_out Rx_OUT = 0 UC Reads Last Data Uc Pooling Rx_out Rx_OUT = 0
HOST Fills USB FIFO ACK OUT Token Rx_OUT = 1
HOST Fills USB FIFO ACK OUT Token Rx_OUT = 1
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Interrupt and Isochronous Transfers
Isochronous transfers use the same protocol with bulk transfers except that error correction and data packet retransmission are not supported: * * * No ACK token No NAK token Data PID is always zero
Interrupt and Interrupt IN Transfers
Suspend
Interrupt transfers use the same protocol with bulk IN transfers (Interrupt OUT is not supported in USB Spec 1.0).
A USB device enters the suspend mode only when requested by the USB host through bus inactivity for at least 3 ms. The USB Hardware detects this request, sets the SUSP bit of the Suspend/Resume Register (SPRSR), and interrupts the processor if the interrupt is enabled. The processor should shutdown any peripheral activity, enter powerdown mode and signal the USB Hardware that it can now enter the suspend mode by w r it ing " 1 " to th e " sle e p mo d e " US B_ Ma cr o in p ut p in. At th is mo me n t, th e "Suspend2SIE" output pin is activated and the oscillator, PLL and other peripherals should be disabled. Resume is signaled by a J- to K-state transition at the USB port. The USB Hardware enables the oscillator/PLL and sets the RSM bit of the SPRSR, which generates an interrupt. The processor starts executing where it left off and services the interrupt. Then the firmware clears the RCVD RSM bit. While the USB peripheral is in suspend mode, resuming is also possible through the remote wake-up feature. Remote wake-up is invoked due to an external event (such as the detection of a key pressing in a keyboard) and is denoted by the "Ext_int" USB_Macro pins (active high). This action, in turn, enables the oscillator and the USB Hardware. The USB Hardware sets the associated flag of UISR and the EXT RSM bit of SPRSR. These generate two interrupts to the processor: Ext_int and RSM_int. The processor starts executing where it left off and services the interrupt. Then the firmware clears the EXT RSM bit and EXT[0-3] bit. If the remote wake-up feature is enabled and the USB bus remains idle for a period of 5 ms (already 3 ms in the suspend mode), the resume signal is sent to the host during the next 10 ms and the RSMINPR bit of the Global State Register is set.
Resume
Remote Wake-up
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AVR Microcontroller
The AT76C711 is based on the AVR architecture and includes many of the features of the AVR AT90S8515 microcontroller. All peripherals, apart from SPI and timers, are memory mapped to the data address space. The interrupt vector table of AT76C711 is shown below. Table 1. AT76C711 Interrupt Vectors
Vector # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Program Address $0000 $0002 $0004 $0006 $0008 $000A $000C $000E $0010 $0012 $0014 $0016 $0018 $001A $001C Source RESET SUSP/RESM INT0 TIMER1 CAPT TIMER1 COMPA TIMER1 COMPB TIMER1 OVF TIMER0 OVF SPI, STC TDMAC UART0 INT RDMAC USB Hardware UART1 INT INT1 Interrupt Definition Hardware Pin and Watchdog Reset USB Suspend and Resume External Interrupt Request 0 Timer/Counter1 Capture Event Timer/Counter1 Compare Match A Timer/Counter1 Compare Match B Timer/Counter1 Overflow Timer/Counter0 Overflow SPI Serial Transfer Complete Tx DMA Termination UART0 Interrupt Request Rx DMA Termination USB Hardware Interrupt UART1 Interrupt Request External Interrupt Request 1
Interrupt Handling
Oscillator and Clock Generator
AT76C711 has two on-chip crystal oscillators. The first one is the main oscillator and is used to generate the clocks of the AVR CPU and the 48 MHz clock of the USB core. The nominal value of this oscillator should be 12 MHz. After the initial reset, the default CPU rate is 24 MHz. Dividing the 48 MHz clock appropriately, an internal clock of 14.746 MHz is produced, which can be used for generating standard modem baud rates with a deviation of 1.6 percent. Alternatively, if a strict baud rate is required, a dedicated oscillator for the UART block is provided. The Clock Tree Circuit is shown in Figure 6. The output pins of the crystal oscillators are not designed to drive any external circuits. Instead of using crystals, either oscillator's input pin can also be driven by an external clock signal.
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Figure 6. Clock Tree Circuit
div 5 XTAL 12 MHz PLL x8 96 MHz IrDA 19.2 MHz UART1 div 4 or 5 cp1, cp2 24 or 19.2 MHz
div 2 div 13/8 (gobbling) UART0 14.7456 MHz UXTAL 14.7456 MHz (Optional) PLL x2 div 2 48 MHz div 4 (DPLL) 12 MHz
div 4
UART0
The main features of UART0 are: * * * * * * * * * * Programmable Baud Rate Generator 16-byte FIFO at the Receiver Side Parity, Framing and Overrun Error Detection Line Break Generation and Detection Automatic Echo, Local Loopback and Remote Loopback Channel Modes Interrupt Generation Two Dedicated Controller Channels 5-, 6-, 7- and 8-bit Character Length Maximum Rate 921.6K Baud Interface to a DMA Controller for Fast Data Transfers to/from the DPRAM
The input to the baud rate generator is selectable between a 14.746 MHz clock (derived from the internal clock generator) or the dedicated UART oscillator. Both the DMA controller and the AVR processor can have access to the UART registers. The arbitration of the UART memory bus is implemented internally to the DMA controller.
Receiver
The UART detects the start of a received character by sampling the RxD signal until it detects a valid start bit. A low level (space) on RxD is interpreted as a valid start bit if it is detected for more than 7 cycles of the sampling clock, which is 16 times the baud rate. Hence a space that is longer than 7/16 of the bit period is detected as a valid start bit. A space that is 7/16 of a bit period or shorter is ignored and the receiver continues to wait for a valid start bit. When a valid start bit has been detected, the receiver samples the RxD at the theoretical midpoint of each bit. It is assumed that each bit lasts 16 cycles of the sampling clock (1 bit period) so the sampling point is 8 cycles (0.5 bit periods) after the beginning of the bit. Therefore, the first sampling point is sampled 24 cycles (1.5 bit periods) after the falling edge of the start bit was detected. Each subsequent bit is sampled 16 cycles (1 bit period) after the previous one.
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Receive FIFO Operation
The 16-byte receive data FIFO is enabled by the (US_FCR) bit 0. The user can set the receiver trigger level. The receiver FIFO section includes a timeout function to ensure data is delivered to the external CPU. An interrupt is generated whenever the Receive Holding Register (US_RHR) has not been read after the loading of a character or if the trigger level has been reached. This function allows an idle condition on the RxD line to be detected. The maximum delay for which the UART should wait for a new character to arrive while the RxD line is inactive (high level) is programmed in US_RTO (Receiver Timeout). When this register is set to "0", no timeout is detected. Otherwise, the receiver waits for a first character and then initializes a counter, which decrements at each bit period and is reloaded at each byte reception. When the counter reaches "0", the timeout bit (bit 6) in US_CSR is set. The user can restart waiting for a first character by setting the start timeout bit (bit 4) of US_CR Register. The timeout duration is: Duration = Value x _ 4 _ x _ Bit Period
Timeout
Receive Break
The break condition is detected by the receiver when all data, parity and stop bits are low. At the moment of the low stop bit detection, the receiver asserts receive break (bit 2) in US_CSR. The end of receive break is detected by a high level for at least 2/16 of the bit period. Receive break (bit 2) is also set after the end of break has been detected. The start bit, data bits, parity bit and stop bits are serially shifted, with the least significant bit first, on the falling edge of the serial clock. The number of data bits is selected in the character length field, (bits 7 and 6) in US_PMR. The parity bit is set according to the parity type bit 1 field in US_PMR. The number of stop bits is selected in the number of stop (bits 4, 5) field in US_MR. When a character is written to US_THR (Transmit Holding), it is transferred to the Shift Register as soon as it is empty. When the transfer occurs, the transmit ready (bit 1) in US_CSR is set until a new character is written to US_THR. If the Transmit Shift Register and US_THR are both empty, the transmitter empty (bit 7) in US_CSR is set. The time-guard function allows the transmitter to insert an idle state on the TxD line between two characters. The duration of the idle state is programmed in US _TTG (Transmitter Time-guard). When this register is set to "0", no time-guard is generated. Otherwise, the transmitter holds a high level on TxD after each transmitted byte during the number of bit periods programmed in US_TTG. The transmitter can generate a break condition on the TxD line when the Start Break command (bit 0) is set in US_CR (Control Register). In this case, the characters present in US_THR and in the Transmit Shift Register are completed before the line is held low. To remove this break condition on the TxD line, the Stop Break command (bit 1) in US_CR must be set. The UART generates minimum break duration of one character length. The TxD line then returns to high level (idle state) for at least 12-bit periods to ensure that the end of break is correctly detected. Then the transmitter resumes normal operation. Each status bit in US_CSR has a corresponding bit in US_IER (Interrupt Enable) that controls the generation of interrupts by asserting the UART interrupt line. Any of the Parity, Framing or overrun Error condition generate a line? Error Interrupt. Interrupt sources are given in the register description section.
Transmitter
Time-guard
Transmit Break
Interrupt Generation
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Channel Modes
The UART can be programmed to operate in three different test modes using the field Channel Mode (bits 6 and 7) in US_MR. Automatic echo mode allows bit-by-bit retransmission. When a bit is received on the RxD line, it is sent to the TxD line. Programming the transmitter has no effect. The local loopback mode allows the transmitted characters to be received. TxD and RxD pins are not used and the output of the transmitter is internally connected to the input of the receiver. The RxD pin level has no effect and the TxD pin is held high, as in the idle state. The remote loopback mode directly connects the RxD pin to the TxD pin. The transmitter and the receiver are disabled and have no effect. This mode allows bit-by-bit retransmission.
UART1 - IrDA Codec
The IrDA codec provides an IrDA 1.0 standard interface. It is connected to the SIN and SOUT of UART1. The IRDAMOD Register of the I/O register set selects the operation mode of the IrDA codec. The EN bit activates the module. When it is deactivated, the UART signals are connected directly to the external interface, bypassing the IrDA codec block. Otherwise, it encodes the outgoing and decodes the incoming data from and to the UART1 respectively, according to the IrDA 1.0 standard (3/16 modulation). The MODE bit gives the user the capability to change the modulation scheme from 3/16 pulse width to 4/16. The UART settings should be half-duplex to avoid signal interference. The UART1 register set is similar to that of UART0: its base address is 2030/hex. The IrDA codec transmits a 3/16 pulse width on zeros (0) and nothing on ones (1). In receive operations, it extends the incoming zeros to 16/16 pulse and feeds them reversed to the UART1 SIN (see "IrDA Serial Infrared Physical Layer Specification" at www.irda.org/standards). An internally generated clock of 19.2 MHz makes it possible to use the IrDA module for up to 1.2 Mbps transfer rates (much higher than the typical 115.2 Kbps). This capability offers a simple solution for high-speed infrared communications. The input to the baud rate generator of UART1 is selectable between the 19.2 MHz clock and the clock of the dedicated oscillator for standard modem rates. A typical application of the AT76C711 connection to an external IR Data Transceiver when the IrDA module is enabled is shown in Figure 7. The GPO is a general-purpose output (can be provided from the data ports).
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Figure 7. AT76C711 Connection to External IR Data Transceiver, IrDA Module Enabled
AT76C711 GPO SD/Mode Tx USART1 Rx IrDA 1.0 Codec Tx IR Data Transceiver
Rx
16x CLK Clock Gen. EN MODE
DMA Controller
The DMA controller is able, under firmware control, to transfer data between the DPRAM and the UART, without the intervention of the processor. The DMA controller will interrupt the processor as soon as it transfers the processor-preprogrammed number of bytes. During data transfers from the DMA controller, the Transmit and Receive DMA Status registers are updated with possible errors indicated by the UART. These status registers can be read by the processor, after the DMA controller's interrupt at the end of a block transfer, to report if the block transfer was error free or not. The DMA controller is programmed by the processor to transfer blocks of data between the DPRAM and the UART core. In addition, the UART can be accessed by the processor only through the DMA controller module. Thus, data transfers between the processor and other memory devices are not interrupted when DMA transfers occur. Segmentation and reassembly of the transmitted/received packets through the UART are also executed with the aid of the DMA controller, under firmware control. Reassembly of network packets is implemented by storing the USB packets from a certain endpoint in successive address spaces. The DMA controller is then programmed to consecutively transfer the bytes of the reassembled packet that has been formed. On the other hand, during packet reception from the UART, the processor can program the DMA controller to read a certain number of bytes from the UART's FIFO and store them at a given target address, depending on the packet header. After the end of the DMA transfer, an interrupt is issued by the DMA controller to signal the processor to check for possible errors during this tra nsfer and forward the packet to the EPs of the USB interface. The DMA controller is programmed with the characteristics of a DMA transfer before it is enabled. The only information that is required is the DPRAM target address and the packet length, because it is already aware of the segment boundaries in order to perform wraparound inside the corresponding segment. In addition, status registers provide information related to errors encountered during a DMA transfer. Two of the above sets of registers are implemented, one for each direction.
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Transmit and receive DMAs are performed by polling the TXRDY and RXRDY signals of the UART. A DMA operation consists of reading the UART status registers and accessing the Data Hold Register. Transmit and receive DMA operations can take place simultaneously. Whenever a receive DMA operation is terminated, either normally or by a Receive Character Timeout Interrupt from the UART or forced by the firmware, an internal RDMAC interrupt signal from DMA is issued to the processor. After that, the firmware should read RXTPLL and RXTPLM to be informed about the exact number of the received bytes, possible errors during DMA and the reason for the DMA termination. After a transmit DMA termination, either normally or forced by firmware, an internal TDMAC interrupt signal from the DMA is issued to the processor. After that, the firmware should read TXTPLL and TXTPLM to be informed about the exact number of the transmitted bytes and the reason for DMA termination.
DPRAM Organization
DPRAM organization is related to the length of the packets transferred through UART. The programmer can define segments in the DPRAM address space from DPORG Register of the DMA controller. Memory segmentation facilitates wraparound during DMA transfers. According to the number of segments, the DMA controller can determine the END and START address of each segment so it doesn't need to be informed about the segment boundaries each time a transfer is enabled. The default state is the DPRAM being unsegmented. Details of the possible DPRAM segmentation schemes are given at the description of the DPORG Register of the DMA controller. The AVR uses a 16-bit address bus to have access to 64-Kbyte memory locations. In AT76C711 design this memory is shared among the various peripherals as shown in Figure 8.
Address Space 0000 - 07FF 0800 - 0FFF 1000 - 1FFF 2000 - 201F 2020 - 202F 2030 - 203F 2040 2041 - 2FFF 3000 - 37FF 3800 - 7FFF 8000 - 7FFF 7FFF - FFFF Size 2048 bytes 2048 bytes 4096 bytes 32 bytes 16 bytes 16 bytes 1 byte 4031 bytes 2048 bytes 18432 bytes 16384 bytes 16384 bytes Module SRAM Reserved USB (not all of the locations are used) DMA controller UART0 UART1 Program Memory Control bit Reserved DPRAM Reserved Program SRAM Reserved
Mapping Allocations
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Figure 8. Memory Allocation for On-chip Resources
64-Kbyte Address Space 0000/h SRAM (0-7FF, Rest Reserved) x00 USB Register Set 1FFF/h 2000/h x1F x20 x2F x50 x5F DPRAM 37FF/h 3800/h 32 Bytes(1) DMA Controller 16-byte Addresses for 12 Registers of UART0 16-byte Addresses for 12 Registers of UART1
0FFF/h 1000/h
2FFF/h 3000/h
Reserved
7FFF/h 8000/h *Program for AVR is stored in the 8K x 16-bit program SRAM (Reset vector is kept in address| "0000"). The program memory can be read using the LPM instruction. However, in order to modify that, it is mapped to the peripheral memory address space as follows: Program SRAM* Least significant byte of address "0000" corresponds to byte address 8000/h of the peripheral memory address space. Most significant byte of address "0000" corresponds to byte address 8001/h of the peripheral memory address space and so on. FFFF/h
Note:
1. These register blocks are mapped to any 256-byte boundary (x00) in address space 2000 - 2FFF/h.
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I/O Memory
The I/O space definition of AT76C711 is shown in Table 2. This space is defined in the area $00 - $3F and can be directly accessed by IN and OUT instructions or by ordinary SRAM accesses in the area $20 - $5F. The notation used will be followed in the rest of this document. A more detailed description of the I/O memory space is given in the sections that follow. Table 2. AT76C711 I/O Space
I/O Address (SRAM Address) $3F($5F) $3E($5E) $3D($5D) $39($59) $37($57) $36($56) $35($55) $34($54) $33($53) $32($52) $31($51) $2F($4F) $2E($4E) $2D($4D) $2C($4C) $2B($4B) $2A($4A) $29($49) $28($48) $27($47) $26($46) $21($41) $20($40) $1B($3B) $1A($3A) $19($39) $18($38) $17($37) $16($36) $15($35) Name SREG SPH SPL EIMSK TIMSK TIFR MCUCR MCUSR TCCR0 TCNT0 PRELD TCCR1A TCCR1B TCNT1H TCNT1L OCR1AH OCR1AL OCR1BH OCR1BL ICR1H ICR1L WDTCR IRDAMOD PORTA DDRA PINA PORTB DDRB PINB PORTC Function Status Register Stack Pointer High Stack Pointer Low External Interrupt Mask Register Timer Interrupt Mask Register Timer Interrupt Flag Register MCU General Control Register MCU Status Register Timer0 Control Register Timer0 (8 bits) Pre-load Register Timer1 Control Register A Timer1 Control Register B Timer1 High Byte Timer1 Low Byte Timer1 Output Compare Register A High Byte Timer1 Output Compare Register A Low Byte Timer1 Output Compare Register B High Byte Timer1 Output Compare Register B Low Byte Timer1 Input Capture Register High Byte Timer1 Input Capture Register Low Byte Watchdog Timer Control Register IrDA Control Register Data Register, Port A Data Direction Register, Port A Input Pins, Port A Data Register, Port B Data Direction Register, Port B Input Pins, Port B Data Register, Port C
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Table 2. AT76C711 I/O Space (Continued)
I/O Address (SRAM Address) $14($34) $13($33) $12($32) $11($31) $10($30) $0F($2F) Name CLK_CNTR PERIPHEN PORTD DDRD PIND SPDR Function Clock Control Register Peripheral Enable Register Data Register, Port D Data Direction Register, Port D Input Pins, Port D SPI I/O Data Register
The AVR Status Register - SREG
Bit $3F ($5F) Read/Write 7 I R/W 6 T R/W 5 H R/W 4 S R/W 3 V R/W 2 N R/W 1 Z R/W 0 C R/W SREG
* Bit 7 - I: Global Interrupt Enable When set, the interrupts are enabled. The individual interrupt enable control is performed in the individual mask registers. This bit is cleared by USB Hardware after an interrupt has occurred and is set by the RETI instruction to enable subsequent interrupts. * Bit 6 - T: Bit Copy Storage Bit load (BLD) and bit store (BST) instructions use the T-bit as source and destination for the operated bit. * Bit 5 - H: Half-carry Flag Indicates a half-carry in some arithmetic operations. * Bit 4 - S: Sign Bit, S = N XOR V Is an exclusive OR between the negative flag N and the two's complement overflow flag V. * Bit 3 - V: Two's Complement Overflow Flag Supports two's complement arithmetic. * Bit 2 - N: Negative Flag When set, indicates a negative result in arithmetic and logic operations. * Bit 1 - Z: Zero Flag When set, indicates a zero result after the different arithmetic and logic operations. * Bit 0 - C: Carry Flag When set, indicates a carry in the arithmetic or logic operations.
The Stack Pointer - SP
Bit $3E ($5E) $3D ($5D) 15 SP15 SP7 7 14 SP14 SP6 6 13 SP13 SP5 5 12 SP12 SP4 4 11 SP11 SP3 3 10 SP10 SP2 2 9 SP9 SP1 1 8 SP8 SP0 0 SPH SPL
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The MCU Control Register - MCUCR
Bit $35 ($55) Read/Write Initial Value 7 - R 0 6 - R 0 5 SE R/W 0 4 SM1 R/W 0 3 SM0 R/W 0 2 - R 0 1 - R 0 0 - R 0 MCUCR
The MCU Control Register is a R/W 3-bit register with zero initial value. It consists of the following bits: * Bits 7, 6 - Reserved Bits Always read as zero. * Bit 5 - SE: Sleep Enable When set, enables the MCU to enter sleep mode when the SLEEP instruction is executed. * Bits 4-0 - Reserved Bits These bits always read as zero
MCU Status Register - MCUSR
Bit $35 ($55) Read/Write Initial Value 7 - R 0 6 - R 0 5 - R 0 4 - R 0 3 - R 0 2 - R 0 1 RESWD R/W 0 PORF R/W MCUSR
See bit description
The MCUSR is a 2-bit R/W register that provides information on which reset source caused an MCU reset. * Bits 7..2 - Reserved Bits Always read as zero. * Bit 1 - REWD This flag indicates that an external or power-on reset has occurred. * Bit 0 - PORF: Power-on Reset Flag The following table shows the value of these two bits after the three modes of reset. Table 3. PORF and EXTRF Values after Reset
Reset Source Power-on Reset External Reset Watchdog Reset PORF 1 Unchanged Unchanged EXTRF Undefined 1 Unchanged
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The user program must clear these bits as early as possible. If these bits are cleared before a reset condition occurs, the source of reset can be found by using the following truth table. Table 4. Reset Source Identification
PORF 0 0 1 1 EXTRF 0 1 0 1 Reset Source Watchdog Reset External Reset Power-on Reset Power-on Reset
The External Interrupt Mask Register - EIMSK
Bit $39 ($59) Read/Write Initial Value 7 - R 0 6 - R 0 5 - R 0 4 - R 0 3 POL1 R/W 0 2 POL0 R/W 0 1 INT1 R/W 0 0 INT0 R/W 0 EIMSK
This is a 4-bit R/W register. Its initial value is zero. It is used for masking the external interrupts. * Bits 7..4 - Reserved Bits Always read as zero. * Bit 3 - POL1 Polarity of external interrupt 1. INT1 is active high when this bit is low. * Bit 2 - POL0 Polarity of external interrupt 0. INT0 is active high when this bit is low. * Bit 1 - INT1 If it is set and the 1 bit in the Status Register is set, the external pin interrupt 1 is enabled. * Bit 0 - INT0 If it is set and the 1 bit in the Status Register is set, the external pin interrupt 0 is enabled.
The Timer/Counter Interrupt Mask Register - TIMSK
Bit $37 ($57) R/W Initial Value 7 TOIE1 R/W 0 6 OCIE1A R/W 0 5 OCIE1B R/W 0 4 - R 0 3 TICIE1 R/W 0 2 - R 0 1 TOIE0 R/W 0 0 - R 0 TIMSK
External interrupts should be acknowledged using general-purpose output pins. This is an 8-bit R/W register with zero initial value, used for masking the internal timer interrupts. * Bit 7 - TOIE1: Timer/Counter1 Overflow Interrupt Enable When this bit is set and the I-bit in the Status Register is one, the Timer/Counter1 Overflow Interrupt is enabled. The corresponding interrupt (at vector $001C) is executed if an overflow in Timer/Counter1 occurs. The Timer/Counter1 Overflow flag is set in the Timer/Counter1 Interrupt Flag Register - TIFR.
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* Bit 6 - OCIE1A: Timer/Counter1 Output Compare A Match Interrupt Enable When this bit is set and the I-bit in the Status Register is one, the Timer/Counter1 Compare A Match Interrupt is enabled. The corresponding interrupt (at vector $0018) is executed if a Compare A match in Timer/Counter1 occurs. The Compare A flag in Timer/Counter1 is set in the Timer/Counter Interrupt Flag Register - TIFR. * Bit 5 - OCIE1B: Timer/Counter1 Output Compare B Match Interrupt Enable When this bit is set and the I-bit in the Status Register is one, the Timer/Counter1 Compare B Match Interrupt is enabled. The corresponding interrupt (at vector $001A) is executed if a Compare B match in Timer/Counter1 occurs. The Compare B flag in Timer/Counter1 is set in the Timer/Counter Interrupt Flag Register - TIFR. * Bit 4 - Reserved Bit * Bit 3 - TICIE1: Timer/Counter1 Input Capture Interrupt Enable When this bit is set and the I-bit in the Status Register is one, the Input Capture Event Interrupt is enabled. The corresponding interrupt (at vector $0016) is executed if a capture event occurs on pin PD2. The Input Capture flag in Timer/Counter1 is set in the Timer/Counter Interrupt Flag Register - TIFR. * Bit 2 - Reserved Bit * Bit 1 - TOIE0: Timer/Counter0 Overflow Interrupt Enable When this bit is set and the I-bit in the Status Register is one, the Timer/Counter0 Overflow Interrupt is enabled. The corresponding interrupt (at vector $0020) is executed if an overflow in Timer/Counter0 occurs. The Timer/Counter0 Overflow flag is set in the Timer/Counter1 Interrupt Flag Register - TIFR.
The Timer/Counter Interrupt Flag Register - TIFR
Bit $36 ($56) R Initial Value 7 TOV1 R/W 0 6 OCFA R/W 0 5 OCFB R/W 0 4 - R 0 3 ICF1 R/W 0 2 - R 0 1 TOV0 R/W 0 0 - R 0 TIFR
* Bit 6 - OCFA: Output Compare Flag A The OCFA is set when a compare match between Timer/Counter1 and the OCR1A Register occurs. This flag is cleared when written with a logic "1". * Bit 5 - OCFB: Output Compare Flag 1B The OCF1B is set when a compare match between Timer/Counter1 and the OCR1B Register occurs. This flag is cleared when written with a logic "1". * Bit 4 - Reserved Bit * Bit 3 - ICF1: Input Capture Flag This flag, when set, indicates an input capture event, where the contents of the Timer/Counter1 are transferred to the ICR1 Register. This flag is cleared when written with a logic "1". * Bit 2 - Reserved Bit * Bit 1 - TOV0: Timer/Counter1 Overflow Flag The TOV0 is set when an overflow occurs in Timer/Counter0. This flag is cleared when written with a logic "1".
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* Bit 0 - Reserved Bit
The Timer/Counter0 Control Register - TCCR0
Bit $33 ($53) Read/Write Initial Value 7 - R 0 6 - R 0 5 - R/W 0 4 - R/W 0 3 - R/W 0 2 CS02 R/W 0 1 CS01 R/W 0 0 CS00 R/W 0 TCCR0
Bits 2-0 of TCCR0 register control the prescaling of the Timer0 clock according to Table 5. Table 5. Timer0 Prescale Select
CS02 0 0 0 0 1 1 1 1 Note: 1. clk = 24 MHz CS01 0 0 1 1 0 0 1 1 CS00 0 1 0 1 0 1 0 1 Description Timer 0 is stopped clk clk/8 (3 MHz)(1) clk/64 clk/256 clk/1024 External Pin PB0, rising edge External Pin PB0, falling edge
The Timer/Counter0 - 0
Bit $32 ($52) 15 MSB 7 Read/Write Initial Value R/W 0 6 R/W 0 5 R/W 0 4 R/W 0 3 R/W 0 2 R/W 0 1 R/W 0 14 13 12 11 10 9 8 LSB 0 R/W 0 TCNT0
This Timer/Counter consists of 8 bits which can be written by the AVR with any initial value to start count from. When this counter is enabled (by writing the CS0[2:0] bits of the TCCR0 with the appropriate value), it starts counting up to 0xFF and when overflowed it is loaded with the value of the PRELD register.
Pre-load Register - PRELD
Bit $31 ($51) Read/Write Initial Value 7 MSB R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 6 5 4 3 2 1 0 LSB R/W 0 PRELD
An 8-bit R/W register with zero initial value. The contents of this register are loaded to Timer/Counter0 (TCNT0) after an overflow of Timer/Counter0 occurs.
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The Timer/Counter1 Control Register A - TCCR1A
Bit $2F ($4F) Read/Write Initial Value 7 COM11 R/W 0 6 COM1A0 R/W 0 5 COM1B1 R/W 0 4 COM1B0 R/W 0 3 - R 0 2 - R 0 1 - R 0 0 - R 0 TCCR1A
This is an 8-bit R/W register with zero initial value. It controls the action taken by the specific output pin on compare match A or B that supports Timer1. The functionality of the bits is as follows: * Bits 7, 6 - COM1A1, COM1A0: Compare Output Mode A These bits cause a specific action for the output compare pin PD6, as shown in Table 6, for Timer0. * Bits 5, 4 - COM1B1, COM1B0 The same holds for Compare Output Mode B and output compare pin PD7, as in the previous case for the Compare Output Mode A. * Bits 3..0 - Reserved Bits Table 6. Compare Mode Select(1)
COM1X1 0 0 1 1 Note: 1. X = A or B COM1X0 0 1 0 1 Description Timer disconnected from output pin Toggle output pin Clear output pin Set output pin
The Timer/Counter Register B - TCCR1B
Bit $2E ($4E) Read/Write Initial Value 7 ICNC1 R/W 0 6 ICES1 R/W 0 5 - R 0 4 - R 0 3 CTC1 R/W 0 2 CS12 R/W 0 1 CS11 R/W 0 0 CS10 R/W 0 TCCR1A
This is an 8-bit R/W register with zero initial value. * Bit 7 - ICNC1: Input Capture1 Noise Canceler (4 CKs) When this bit is zero, the input canceler function is disabled. The input capture is triggered at the first rising/falling edge sampled on the input capture pin PB2, as specified by the ICES1 bit. When this bit is set, four successive samples are measured and all samples must be high/low according to the input capture trigger specification in the ICES1 bit. The actual sampling frequency is the CPU clock frequency. * Bit 6 - ICES1: Input Capture1 Edge Select When this bit is cleared, the Timer/Counter1 contents are transferred to the Input Capture Register - ICR1 on the falling edge of the input capture pin, PB2. When it is "1", the contents are transferred on the rising edge. * Bits 5, 4 - Reserved Bits Always read as zero.
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* Bit 3 - CTC1: Clear Timer/Counter1 on Compare Match When it is "1", the Timer/Counter1 is reset to $0000 after a Compare A match. If it is cleared, the Timer/Counter1 continues counting after a Compare A match. * Bits 2..0 - CS12, CS11 and CS10: Clock Select1, Bits 2, 1 and 0 These bits select prescaling source for the Timer/Counter1 according to Table 7. Table 7. Timer1 Prescale Select
CS12 0 0 0 0 1 1 1 1 Note: 1. X = A or B CS11 0 0 1 1 0 0 1 1 CS10 0 1 0 1 0 1 0 1 Description Timer1 is stopped clk clk/8(1) clk/64 clk/256 clk/1024 External Pin PB1, rising edge External Pin PB1, falling edge
The Timer/Counter1 - TCNT1H and TCNT1L
Bit $2D ($4D) $2C ($4C) 7 Read/Write Initial Value R/W 0 6 R/W 0 5 R/W 0 4 R/W 0 3 R/W 0 2 R/W 0 1 R/W 0 15 MSB LSB 0 R/W 0 14 13 12 11 10 9 8 TCNT1H TCNT1L
This Timer/Counter consists of 16 bits and is made by two 8-bit R/W registers with initial value of zero, namely TCNT1H and TCNT1L. To ensure that both the high and low bytes are read and written simultaneously when the CPU accesses these registers, the access is performed using an 8-bit temporary register (TEMP). This temporary register is also used when accessing OCR1A, OCR1B and ICR1. If the main program and interrupt routines perform accesses to registers using TEMP, interrupts must be disabled during access from the main program.
TCNT1 Timer/Counter1 Write
When the CPU writes to the high byte (TCNT1H), the written data are placed in the TEMP register. Next, when the CPU writes the low byte (TCNT1L), this byte of data is combined with the TEMP register and all 16 bits are written simultaneously to the Timer/Counter1 (TCNT1) Register. Consequently, the high byte must be accessed first for a full 16-bit write operation. When using Timer/Counter1 as an 8-bit counter, it is sufficient to write the low byte only. * TCNT1 Timer/Counter1 Read When the CPU reads the low byte (TCNT1L), the data are placed in the TEMP register. Next, when the CPU reads the high byte (TCNT1H), the CPU receives the data in the TEMP register. Consequently, the low byte must be accessed first for a full 16-bit read operation. When using Timer/Counter1 as an 8-bit counter, it is sufficient to read the low byte only. 30
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The Timer/Counter1 Output Compare Register B - OCR1BH and OCR1BL
Bit $29 ($49) $28 ($48) 7 Read/Write R/W R/W Initial Value 0 0 6 R/W R/W 0 0 5 R/W R/W 0 0 4 R/W R/W 0 0 3 R/W R/W 0 0 2 R/W R/W 0 0 1 R/W R/W 0 0 15 MSB LSB 0 R/W R/W 0 0 14 13 12 11 10 9 8 OCR1BH OCR1BL
This Timer/Counter Output Compare Register B consists of 16 bits and is made by two 8-bit R/W registers with initial value of zero, namely OCR1BH and OCR1BL. Full 16-bit write and read operations are made according to the way specified for the Timer/Counter1 (TCNT1) above.
The Timer/Counter1 Input Capture Register - ICR1H and ICR1L
Bit $27 ($47) $26 ($46) 7 Read/Write R/W R/W Initial Value 0 0 6 R/W R/W 0 0 5 R/W R/W 0 0 4 R/W R/W 0 0 3 R/W R/W 0 0 2 R/W R/W 0 0 1 R/W R/W 0 0 15 MSB LSB 0 R/W R/W 0 0 14 13 12 11 10 9 8 ICR1H ICR1L
This Timer/Counter Output Compare Register consists of 16 bits and is made by two 8-bit R/W registers with initial value of zero, namely ICR1H and ICR1L. Full 16-bit write and read operations are made according to the way specified for the Timer/Counter1 (TCNT1) above.
The Watchdog Timer Control Register - WDTCR
Bit $21 ($41) Read/Write Initial Value 7 - R 0 6 - R 0 5 - R 0 4 WDTOE R/W 0 3 WDE R/W 0 2 WDP2 R/W 0 1 WDP1 R/W 0 0 WDP0 R/W 0 WDTCR
This is an 8-bit R/W register with zero initial value. * Bits 7..5 - Reserved Bits Always read as zero. * Bit 4 - WDTOE: Watchdog Turn Off Enable This bit must be set when the WDE bit is cleared. Otherwise, the watchdog will not be disabled. Once set, USB Hardware will clear this bit to zero after four clock cycles.
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* Bit 3 - WDE: Watchdog Enable When this bit is set, the watchdog timer is enabled; when it is zero, the watchdog timer is disabled. WDE can only be cleared when the WDTOE is set. To disable an enabled watchdog timer, the following procedure must be followed: 1. In the same operation, write a logic "1" to WDTOE and WDE. A logic "1" must be written to WDE even though it is set to one before the disable operation starts. 2. Within the next four clock cycles, write a logic "0" to WDE. This disables the watchdog. * Bits 2..0 - WDP2, WDP1, WDP0: Watchdog Timer Prescaler 2, 1 and 0 These bits determine the watchdog timer prescaling when the watchdog timer is enabled according to the following table. Table 8. Watchdog Timer Prescale Register Select
WDP2 0 0 0 0 1 1 1 1 WDP1 0 0 1 1 0 0 1 1 WDP0 0 1 0 1 0 1 0 1 Timeout Period (Cycles) 16K 32K 64K 128K 256K 512K 1024K 2084K
The IRDAMOD Register
Bit $20 ($40) Read/Write Initial Value 0 0 0 0 0 7 6 5 4 3 2 POL R/W 0 1 MODE R/W 0 0 EN R/W 0 IRDAMOD
* Bits 7..3 - Reserved Bits Always read as zero. * Bit 2 - POL Inverts the polarity of P_IRX data input to IrDA encoder. * Bit 1 - MODE When this bit is set, serial data to and from IrDA codec are modulated according to a 4/16 pulse scheme. Otherwise, a logic "0" is denoted by a positive pulse, which remains high for 3 pulses of the 16x baud clock while a logic "1" is denoted by a low-level signal for 16 pulses of the 16x baud clock. * Bit 1 - EN When reset, IrDA codec is bypassed.
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I/O Ports
Port A
Port A is an 8-bit bi-directional I/O port with internal pull-up resistors.
The Port A Data Register - PORTA
Bit
7 PORTA7 R/W 0
6 PORTA6 R/W 0
5 PORTA5 R/W 0
4 PORTA4 R/W 0
3 PORTA3 R/W 0
2 PORTA2 R/W 0
1 PORTA1 R/W 0
0 PORTA0 R/W 0 PORTA
$1B ($3B) Read/Write Initial Value
The value of any PORTAx bit is the voltage level to the corresponding pad of PORTA, when the DDRAx bit is high; x = 0..7
The Port A Data Direction Register - DDRA
Bit $1A ($3A) Read/Write Initial Value 7 DDA7 R/W 0 6 DDA6 R/W 0 5 DDA5 R/W 0 4 DDA4 R/W 0 3 DDA3 R/W 0 2 DDA2 R/W 0 1 DDA1 R/W 0 0 DDA0 R/W 0 DDRA
The Port A Data Direction Register controls the direction of the Port A pins. When bit DDRAx is set, then PAx pin is output; when DDRAx is cleared, PAx is input; x = 0..7.
The Port A Input Pins Address - PINA
Bit $19 ($39) Read/Write Initial Value 7 PINA7 R/W 1 6 PINA6 R/W 1 5 PINA5 R/W 1 4 PINA4 R/W 1 3 PINA3 R/W 1 2 PINA2 R/W 1 1 PINA1 R/W 1 0 PINA0 R/W 1 PINA
The Port A Input Pins Address (PINA) is not a physical register. Instead, this address enables access to the physical voltage value on each port pin. It is a read-only address. On power up, PORTA is an input port and a read of PINA register returns an all-1 value due to the pull-up resistors of the PORTA.
Port B
Port B is an 8-bit bi-directional I/O port with internal pull-ups.
The Port B Data Register - PORTB
Bit $18 ($38) Read/Write Initial Value 7 PORTB7 R/W 0 6 PORTB6 R/W 0 5 PORTB5 R/W 0 4 PORTB4 R/W 0 3 PORTB3 R/W 0 2 PORTB2 R/W 0 1 PORTB1 R/W 0 0 PORTB0 R/W 0 PORTB
The value of any PORTBx bit is the voltage level to the corresponding pad of PORTB, when the DDRBx bit is high; x = 0..7
The Port B Data Direction Register - DDRB
Bit $17 ($37) Read/Write Initial Value 7 DDB7 R/W 0 6 DDB6 R/W 0 5 DDB5 R/W 0 4 DDB4 R/W 0 3 DDB3 R/W 0 2 DDB2 R/W 0 1 DDB1 R/W 0 0 DDB0 R/W 0 DDRB
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The Port B Data Direction Register controls the direction of the Port B pins. When bit DDRBx is set, then PBx pin is output; when DDRBx is cleared, PBx is input; x = 0..7.
The Port B Input Pins Address - PINB
Bit $16 ($36) Read/Write Initial Value 7 PINB7 R/W High-Z 6 PINB6 R/W High-Z 5 PINB5 R/W High-Z 4 PINB4 R/W High-Z 3 PINB3 R/W High-Z 2 PINB2 R/W High-Z 1 PINB1 R/W High-Z 0 PINB0 R/W High-Z PINB
The Port B Input Pins Address (PINB) is not a physical register. This address enables access to the physical voltage value on each port pin. It is a read-only address. On power up, PORTA is an input port and a read of PINA register returns an all-1 value due to the pull-up resistors of the PORTA. Port B, besides its use as a general-purpose I/O port, is used to support alternate functions. Specifically, the SPI interface, the input capture pin for Timer/Counter1 and the external clocks for the Timer/Counters are implemented through Port B, according to the following table. Table 9. Port B Pins Alternate Functions
Port Pin PB0 PB1 PB2 PB4 PB5 PB6 PB7 Alternate Functions External Clock Pin for Timer/Counter0 External Clock Pin for Timer/Counter1 Input Capture Pin for Timer/Counter1 SS (SPI Slave Select Input) MOSI (SPI Bus Master Output/Slave Input) MISO (SPI Bus Master Input/Slave Output) SCK (SPI Bus Serial Clock)
Port C
Port C is a 4-bit output port.
The Port C Data Register - PORTC
Bit $15 ($35) Read/Write Initial Value 7 - R 0 6 - R 0 5 - R 0 4 - R 0 3 PORTC3 R/W 0 2 PORTC2 R/W 0 1 PORTC1 R/W 0 0 PORTC0 R/W 0 PORTC
The value of any PORTCx bit controls directly the voltage level of PCx; x = 0..4
Clock Control Register - CLK_CNTR
Bit $14 ($34) Read/Write Initial Value R 0 R 0 R 0 7 6 5 4 UOSC R/W 0 3 UCK R/W 0 2 IrCK R/W 0 R/W 0 R/W 0 1 0 CLK_CNTR
This is a 5-bit R/W register that is used for controlling the clocks of the peripheral components and the speed of the MCU.
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* Bits 7..5 - Reserved Always read as zero. * Bit 4 - UOSC Enables UART oscillator when set. * Bit 3 - UCK Select clock source for UART0 module. When cleared, the 16x (baud rate) clock input of the UART0 is the gobbling clock generated from the 24 MHz clock after divided by 13/8 as shown in Figure 6. All standard UART rates up to 921K baud can be supported. When this bit is set, the UART0 16x (baud rate) clock frequency is that of the UOSC provided that UOSC bit is also set. * Bit 2 - IrCK Select clock source for UART1 - IrDA module. When cleared, the 16x (baud rate) clock input of the UART1 is 19.2 MHz derived from the division of 96 MHz by 5, as shown in Figure 6. When this bit is set, the UART1 16x (baud rate) clock frequency is that of the UOSC provided that UOSC bit is also set. * Bits 1, 0 - Reserved These bits should be set to zero.
Peripheral Enable Control Register - PERIPHEN
Bit $13 ($33) Read/Write Initial Value R 0 R 0 R/W 0 R/W 0 R/W 0 7 6 5 4 3 2 IRDA R/W 0 1 UART R/W 0 0 USB R/W 0 PERIPHEN
A 6-bit R/W register that enables the peripheral components of the system, such as SPI, UART and USB. * Bits 7, 6 - Reserved Bits Always read as zero. * Bits 5..3 - Reserved Bits * Bit 2 - IRDA When set, enables the function of IrDA. * Bit 1 - UART When set, enables the function of UART. * Bit 0 - USB When set, enables the function of USB (clock enable).
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Port D
Port D is an 8-bit bi-directional I/O port. Note that the PORTD pins 7 and 6 have internal pull down resistors while the rest have internal pull-ups.
The Port D Data Register - PORTD
Bit $12 ($32) Read/Write Initial Value 7 PORTD7 R/W 0 6 PORTD6 R/W 0 5 PORTD5 R/W 0 4 PORTD4 R/W 0 3 PORTD3 R/W 0 2 PORTD2 R/W 0 1 PORTD1 R/W 0 0 PORTD0 R/W 0 PORTD
The value of any PORTDx bit is the voltage level to the corresponding pad of PORTD, when the DDRDx bit is high; x = 0..7.
The Port D Data Direction Register - DDRD
Bit $11 ($31) Read/Write Initial Value 7 DDD7 R/W 0 6 DDD6 R/W 0 5 DDD5 R/W 0 4 DDDD4 R/W 0 3 DDD3 R/W 0 2 DDD2 R/W 0 1 DDD1 R/W 0 0 DDD0 R/W 0 DDRD
The Port D Data Direction Register controls the direction of the Port D pins. When bit DDRDx is set, then PDx pin is output; when DDRDx is cleared, PDx is input; x = 0..7.- Table 10. Port D Pins Alternate Functions
Port Pin PD0 PD1 PD6 PD7 Alternate Functions UART Receive Input UART Transmit Output External Interrupt Input0 External Interrupt Input1
The Port D Input Pins Address - PIND
Bit $10 ($39) Read/Write Initial Value 7 PIND7 R/W 0 6 PIND6 R/W 0 5 PIND5 R/W 1 4 PIND4 R/W 1 3 PIND3 R/W 1 2 PIND2 R/W 1 1 PIND1 R/W 1 0 PIND0 R/W 1 PIND
The Port D Input Pins Address (PIND) is not a physical register. Instead, this address enables access to the physical voltage value on each port pin. It is a read-only address. On power up, PORTD is an input port and a read of PIND register returns an all-1 value for PIND 5 - 0 due to the pull-up resistors of the those pins and zero for PIND6, PIND7 due to their pull down resistors.
The SPI Control Register - SPCR
Bit $0D ($2D) Read/Write Initial Value 7 SPIE R/W 0 6 SPE R/W 0 5 DORD R/W 0 4 MSTR R/W 0 3 CPOL R/W 0 2 CPHA R/W 0 1 SPR1 R/W 0 0 SPR0 R/W 0 SPCR
An 8-bit R/W register with zero initial value.
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* Bit 7 - SPIE: SPI Interrupt Enable This bit causes setting of the SPIF bit in the SPSR Register to execute the SPI Interrupt provided that global interrupts are enabled. * Bit 6 - SPE: SPI Enable When it is set, the SPI is enabled and SS, MOSI, MISO and SCK are connected to pins PB4, PB5, PB6 and PB7. * Bit 5 - DORD: Data Order When it is "1", the LSB of the data word is transmitted first. When it is cleared, the MSB of the data word is transmitted first. * Bit 4 - MSTR: Master/Slave Select This bit selects Master SPI when set and Slave SPI mode when cleared. If SS is configured as input and is driven low while MSTR is set, MSTR will be cleared and SPIF in SPSR will become set. The user will then have to set MSTR to re-enable SPI master mode. * Bit 3 - CPOL: Clock Polarity When this bit is set, SCK is high when idle. When CPOL is cleared, SCK is low when idle. * Bit 2 - CPHA: Clock Phase When set, the data is valid in the falling edge of SCK if CPOL = 0, or in the rising edge of SCK when CPOL = 1. When cleared, data are valid in the rising edge of SCK if CPOL = 0 and in the falling edge of SCK if CPOL = 1. * Bits 1, 0 - SPR1, SPR0: SPI Clock Rate Select 1 and 0 These two bits control the SCK rate of the device configured as a master. SPR1 and SPR0 have no effect on the slave. The relationship between the slave and the oscillator clock frequency ( f cl ) is shown in the following table.. Table 11. Relationship between SCK and the Oscillator Frequency
SPR1 0 0 1 1 SPR0 0 1 0 1 SCG Frequency f cl /4 f cl /16 f cl /64 f cl /128
The SPI Status Register - SPSR
Bit $0E ($2E) Read/Write Initial Value 7 SPIF R 0 6 WCOL R 0 5 - R 0 4 - R 0 3 - R 0 2 - R 0 1 - R 0 0 - R 0 SPSR
This is an 8-bit read register with zero initial value. * Bit 7 - SPIF: SPI Interrupt Flag When a serial transfer is complete, the SPIF bit is set and an interrupt is generated if SPIE in SPCR is set and global interrupts are enabled. Alternatively, the SPIF bit is cleared by first reading the SPI Status Register with SPIF set, then by accessing the SPI Data Register.
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* Bit 6 - WCOL: Write Collision Flag The WCOL bit is set if the SPI Data Register (SPDR) is written during a data transfer. During data transfer, the result of reading the SPDR may be incorrect, and writing to it will have no effect. The WCOL bit (and the SPIF bit) are cleared by first reading the SPI Status Register with WCOL set, and then by accessing the SPI Data Register. * Bits 5..0 - Reserved Always read as zero.
The SPI Data Register
Bit $0F ($2F) Read/Write Initial Value 7 MSB R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 6 5 4 3 2 1 0 LSB R/W 0 SPDR
An 8-bit R/W register with zero initial value. It is used for data transfer between the register file and the SPI Shift Register. Writing to the register initiates data transmission. Reading the register causes the Shift Register Receive buffer to be read.
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Data Memory Peripherals - Register Description
UART Register Set
There are two sets of the following registers one for each UART. For UART0, the base address for those registers is 2020/hex while for UART1 the base address is 2050/hex. In Table 12, the register file and its fields are briefly presented. A more detailed description is provided in the following sections. Table 12. UART Register File and Register Fields
Offset Addr. A[3:0] 0000 0000 0001 Register [default] US_RHR US_THR US_IER Bit 7 X X Transmitter Empty Interrupt RCVR Trigger (MSB) Character Length (MSB) Channel Mode (CHM1) Transmitter Empty Bit 6 X X Receive Timeout Interrupt RCVR Trigger (LSB) Character Length (LSB) Channel Mode (CHM0) Receive Timeout Reset Status Bit 0 Number of Stop Bits (MSB) 0 0 Number of Stop Bits (LSB) 0 Bit 5 X X Bit 4 X X Bit 3 X X Line Error Interrupt DMA Mode Select Parity Mode (PTM2) 0 Bit 2 X X Receive Break Interrupt 0 Parity Mode (PTM1) 0 Bit 1 X X Transmit Holding Register RCVR FIFO Reset Parity Type (PT) Bit0 X X Receive Holding Register FIFO Enable
0010
US_FCR(1)
0011
US_PMR
0
0100
US_MR
0 Transmit Holding Register Ready Stop Break
0 Receive Holding Register Ready Start Break LSB LSB LSB LSB
0101
US_CSR
Parity Error
Framing Error Restart Timeout
Overrun Error
Receive Break
0110 0111 1000 1001 1010
US_CR US_BL US_BM US_RTO US_TTG
Rx Enable MSB MSB MSB MSB
Tx Enable
Tx Reset
Rx Reset
Note:
1. This Register is not available for UART1 and should not be written.
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Receive Holding Register - US_RHR
Bit $0 Read/Write Initial Value 7 MSB W 0 W 0 W 0 W 0 W 0 W 0 W 0 6 5 4 3 2 1 0 LSB W 0 US_RHR
Transmit Holding Register - US_THR
Bit $0 Read/Write Initial Value 7 MSB R 0 R 0 R 0 R 0 R 0 R 0 R 0 6 5 4 3 2 1 0 LSB R 0 US_THR
Interrupt Enable Register - US_IER
Bit $1 Read/Write Initial Value 7 TXEI R/W 0 6 RXTOI R/W 0 5 Res R/W 0 4 Res R/W 0 3 RLEI R/W 0 2 RBRI R/W 0 1 THRI R/W 0 0 RHRI R/W 0 US_IER
* Bit 7 - Transmitter Empty Interrupt When set, the interrupt is enabled. When both the Transmit Holding Register (US_THR) and the Transmit Shift Register are empty and the I-bit in the Status Register (SREG) of the MCU is set, an interrupt will occur. * Bit 6 - Receive Timeout Interrupt When set, the Timeout Interrupt is enabled. When the timeout period for the receiver has passed and the I-bit in the Status Register (SREG) of the MCU is set, an interrupt will occur. * Bit 5 - Reserved * Bit 4 - Reserved * Bit 3 - Line Error Interrupt This bit, when set, enables the Line Error Interrupt. If the I-bit in the Status Register (SREG) of the MCU is set, an interrupt will occur at a line error. * Bit 2 - Receive Break Interrupt When set, enables Receive Break Interrupt. If a receive break condition is detected and both this and the I-bit of SREG of the MCU is set, an interrupt will occur. * Bit 1 - Transmit Holding Register Interrupt When set, indicates that the Transmit Ready Interrupt is enabled. When the contents of the Transmit Holding Register are transferred to the Transmit Shift Register and both this and the I-bit of SREG of the MCU are set, an interrupt occurs. * Bit 0 - Receive Holding Register Interrupt When set, indicates that the Receive Holding Register Interrupt is enabled. If the data loaded in the Receive Holding Register (US_RHR) are not read or the trigger level has been reached, an interrupt occurs if this bit and the I-bit of the SREG of the MCU are set.
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FIFO Control Register - US_FCR
Bit $2 Read/Write Initial Value 7 RCVR1 R/W 0 6 RCVR0 R/W 0 5 Res R/W 0 4 Res R/W 0 3 RDMA R/W 0 2 Res R/W 0 1 FRS R/W 0 0 FEN R/W 0 US_FCR
* Bits 7, 6 - RCVR Trigger Bits These bits indicate the minimum number of bytes required in the receive FIFO to generate a Receive Ready Interrupt. The trigger level is shown in the following table.
Bit 7 0 0 1 1 Bit 6 0 1 0 1 Trigger Level 1 4 8 14
* Bit 5 - Reserved * Bit 4 - Reserved * Bit 3 - DMA Mode Select When set, the DMA is in burst mode according to the value in US_FCR. When it is cleared, the characters are read one byte each time. * Bit 2 - Reserved * Bit 1 - FIFO Reset When set, resets the receive FIFO. * Bit 0 - FIFO Enable When set, enables the 16-byte receive FIFO.
Protocol Mode Register - US_PMR
Bit $3 Read/Write Initial Value 7 CHL1 R/W 0 6 CHL0 R/W 0 5 SBN1 R/W 0 4 SBN0 R/W 0 3 PM1 R/W 0 2 PM0 R/W 0 1 Res R/W 0 0 LSB R/W 0 US_PMR
* Bits 7, 6 - Character Length These bits determine the character length, according to the following table.
Bit 7 0 0 1 Bit 6 0 1 0 Character Length 5 6 7
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* Bits 5, 4 - Number of Stop Bits These bits determine the number of stop bits, according to the following table.
Bit 5 0 0 1 1 Bit 4 0 1 0 1 Number of Stop Bits 1 1.5 2 Reserved
* Bits 3-1 - Parity Mode These bits determine the parity mode, according to the following table.
Bit 3 0 0 0 0 1 Bit 2 0 0 1 1 x Bit1 0 1 0 1 x Parity Mode Even Parity Odd Parity Space Mark No Parity
* Bit 0 - Reserved
Mode Register - US_MR
Bit $4 Read/Write Initial Value 7 CHM1 R/W 0 6 CHM0 R/W 0 5 Res R/W 0 4 Res R/W 0 3 Res R/W 0 2 Res R/W 0 1 Res R/W 0 0 Res R/W 0 US_MR
* Bits 7, 6 - Channel Mode These bits determine the channel mode, according to the following table.
Bit 7 0 0 1 1 Bit 6 0 1 0 1 Channel Mode Normal Mode Automatic Echo Mode Local Loopback Mode Remote Loopback Mode
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* Bit 5 - Reserved
Control Status Register- US_CR
Bit $5 Read/Write Initial Value 7 TXE R/W 0 6 RXTO R/W 0 5 PE R/W 0 4 FE R/W 0 3 OE R/W 0 2 RBR R/W 0 1 THR R/W 0 0 RHR R/W 0 US_CSR
* Bit 7 - Transmitter Empty When set, indicates that both the Transmit Holding Register (US_THR) and Transmit Shift Register are empty. * Bit 6 - Receive Timeout When set, indicates that a receive timeout condition has occurred. * Bit 5 - Parity Error When set, indicates that a parity error has occurred. * Bit 4 - Framing Error When set, indicates that a framing error has occurred (start or stop bits have been received with errors). * Bit 3 - Overrun Error When set, indicates that an overrun error has occurred. This means that the Receive Holding Register is being written with a new value, while the previous one has not been read. * Bit 2 - Receive Break When set, indicates that a break condition has occurred during reception. * Bit 1 - Transmit Holding Register Ready When set, indicates that the contents of the Transmit Holding Register have been transferred to the Transmit Shift Register. * Bit 0 - Receive Holding Register Ready When set, indicates that the Receive Holding Register is full.
Control Register - US_CR
Bit $6 Read/Write Initial Value 7 RXEN R/W 0 6 RLES R/W 0 5 TXEN R/W 0 4 RSTO R/W 0 3 TXRS R/W 0 2 RXRS R/W 0 1 SPB R/W 0 0 STB R/W 0 US_CR
* Bit 7 - Rx Enable When set, enables the receiver block of UART. * Bit 6 - Reset Line Error Status Bit When set, resets the PE, FE, OE bits of US_CSR. * Bit 5 - Tx Enable When set, enables the transmitter block of UART. * Bit 4 - Restart Timeout When set, resets the timeout counter for a new timeout period.
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* Bit 3 - Tx Reset When set, resets the transmit logic. * Bit 2 - Rx Reset When set, resets the receive logic. * Bit 1 - Stop Break Break command to the transmit logic. When set, stops break condition. * Bit 0 - Start Break Break command to the transmit logic. When set, starts break condition.
Baud Rate Register, Low Byte - US_BL
Bit $7 Read/Write Initial Value 7 MSB R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 6 5 4 3 2 1 0 LSB R/W 0 US_BL
Baud Rate Register, High Byte - US_BM
Bit $8 Read/Write Initial Value 7 MSB R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 6 5 4 3 2 1 0 LSB R/W 0 US_BM
Receiver Timeout Register - US_RTO
Bit $9 Read/Write Initial Value 7 MSB R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 6 5 4 3 2 1 0 LSB R/W 0 US_RTO
This register contains the maximum period for which the UART can wait before a character arrives during the timeout function. This function is disabled when this register is zero. The value of register US_RTO represents bit periods.
Transmitter Time-guard Register - US_TTG
Bit $A Read/Write Initial Value 7 MSB R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 6 5 4 3 2 1 0 LSB R/W 0 US_TTG
The value of this register indicates the delay (in bit periods) that an active transmitter has to interpose between two consecutive character transmissions.
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Table 13. Baud Rate Generation Example (Clock = 14,7456 MHz)
Output Baud Rate 100 200 400 600 1200 2400 4800 9600 19200 38400 57.6k 76.81 153.6k 307.2k 460.8k 921.6k User Divisor (16 * clk) (Decimal) 9216 4608 2304 1536 768 384 192 96 48 24 16 12 6 3 2 1 (Hex) 2400 1200 900 600 300 180 C0 60 30 18 10 0C 06 03 02 01 UBM Value (Hex) 24 12 09 06 03 01 00 00 00 00 00 00 00 00 00 00 UBL Value (Hex) 00 00 00 00 00 80 C0 60 30 18 10 0C 06 03 02 01
DMA Controller Register Set
The base address for the DMA register file is 2000/hex. The following sections describe the bits of the registers of the DMA controller.
TXTADL - Transmit DMA Target Address LSBs
Register Address: Default State:
Bit 7 6-4 3-0
0x2001 0x00
Mnemonic TXDMAEN Reserved TXTAD[11:8] Most significant bits of the 12-bit transmit DMA target address Description Transmit DMA enable
TXPLL - LSBs of Packet Length during Direct Memory Readings
Register Address: Default State:
Bit 7-0
0x2003 0x00
Mnemonic TXPL[7:0] Description Least significant bits of the 11-bit transmit packet length field
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TXPLM - MSBs of Packet Length during Direct Memory Readings
Register Address: Default State:
Bit 7-3 2-0
0x2004 0x00
Mnemonic Reserved TXPL[10:8] Most significant bits of the 11-bit transmit packet length field Description
TXTPLL - LSBs of the Number of Bytes Transmitted during the Last Transmit DMA
Register Address: Default State:
Bit 7-0
0x2005 0x00
Mnemonic TXTPL[7:0] Description Least significant bits of the number of bytes transmitted during the last transmit DMA operation
TXTPLM - MSBs of the Number of Bytes Transmitted during the Last Transmit DMA and Transmit Status Information
Register Address: Default State:
Bit 7-5 4 TCOM
0x2006 0x00
Mnemonic Description Transmit status information (to be defined) DMA has normally terminated after transmitting the requested number of bytes. Cleared when this register is read. Host has ceased a transmit DMA before the requested buffer size is transmitted. Cleared when this register is read. Most significant bits of the number of bytes transmitted during the last transmit DMA operation
3
TNCOM
2-0
TXTPL[10:8]
RXTADL - Received DMA Target Address LSBs
Register Address: Default State:
Bit 7-0
0x2007 0x00
Mnemonic RXTAD[7:0] Description Least significant bits of the 12-bit receive DMA target address
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RXTADMEN - Receive DMA Target Address MSBs, DMA Enable
Register Address: Default State:
Bit 7 6-4 3-0
0x2008 0x00
Mnemonic RXDAMAEN Reserved RXTAD[11:8] Most significant bits of the 12-bit receive DMA target address Description Receive DMA enable
RSPLL - LSBs of Packet Length during Direct Memory Writings
Register Address: Default State:
Bit 7-0
0x2009 0x00
Mnemonic RXPL[7:0] Description Least significant bits of the 11-bit receive packet length field
RXPLM - MSBs of Packet Length during Direct Memory Writings
Register Address: Default State:
Bit 7-3 2-0
0x200A 0x00
Mnemonic Reserved RXPL[10:8] Most significant bits of the 11-bit receive packet length field Description
RXTPLL - LSBs of the Number of Bytes Received during the Last Receive DMA
Register Address: Default State:
Bit 7-0
0x200B 0x00
Mnemonic RXTPL[7:0] Description Least significant bits of the number of the received bytes during the last receive DMA operation
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RXTPLM - MSBs of the Number of Bytes Received during the Last Receive DMA and Receive Status Information
Register Address: Default State:
Bit 7
0x200C 0x00
Mnemonic RER Description At least one error (parity, framing, overrun) occurred during packet reception. Cleared when a new receive DMA is programmed.
6 5 4
Reserved Reserved RCOM DMA has normally terminated after receiving the requested number of bytes. Cleared when this register is read. The processor has ceased DMA before receiving the expected number of bytes. Cleared when this register is read. Most significant bits of the number of the received bytes during the last receive DMA operation
3
RNCOM
2-0
RXTPL[10:8]
INTCST - Interrupt Control and Status Register
Register Address: Default State:
Bit 7-4 3
0x200D 0x00
Mnemonic Reserved DTXIRQ This bit indicates that a Transmit DMA Interrupt request is pending. This bit is cleared and the corresponding interrupt is acknowledged when the RXTPLM Register is read. This bit indicates that a Receive DMA Interrupt request is pending. This bit is cleared and the corresponding interrupt is acknowledged when the RXTPLM Register is read. Enables Transmit DMA interrupts Enables Receive DMA interrupts Description
2
DRXIRQ
1 0
TXINTE RXINTE
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USB Register Set
The USB appears to the AVR just like another peripheral. The USB register file is mapped to the SRAM space. Table 14 summarizes the USB cell-specific registers. Table 14. USB Register Set
Register FRM_NUM_H FRM_NUM_L GLB_STATE SPRSR SPRSIE UISR UIAR UIER FADDR ENDPPGPG ECR0 ECR1 ECR2 ECR3 ECR4 ECR5 ECR6 CSR0 CSR1 CSR2 CSR3 CSR4 CSR5 CSR6 FDR0 FDR1 FDR2 FDR3 FDR4 FDR5 FDR6 FBYTE_CNT0_L FBYTE_CNT1_L Address 0x0FD 0x0FC 0x0FB 0x0FA 0x0F9 0x0F7 0x0F5 0x0F3 0x0F2 0x0F1 0x0EF 0x0EE 0x0EC 0x0EC 0x0EB 0x0EA 0x0E9 0x0DF 0x0DE 0x0DD 0x0DC 0x0DB 0x0DA 0x0D9 0x0CF 0x0CE 0x0CD 0x0CC 0x0CB 0x0CA 0x0C9 0x0BF 0x0BE Default xxxxx000 xxxxx000 xxxxx000 xxxxx000 xxxxx000 00000000 xxxxx000 00000000 00000000 00000000 0xxx0000 0xxx0000 0xxx0000 0xxx0000 0xxx0000 0xxx0000 0xxx0000 x1110000 x1110000 x1110000 x1110000 x1110000 x1110000 x1110000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 Function Frame Number High Register Frame Number Low Register Global State Register Suspend/Resume Register Suspend/Resume Interrupt Enable Register USB Interrupt Status Register USB Interrupt Acknowledge Register USB Interrupt Enable Register for all EPs Function Address Register Function Endpoint Ping-pong Register Endpoint0 Control Register Endpoint1 Control Register Endpoint2 Control Register Endpoint3 Control Register Endpoint4 Control Register Endpoint5 Control Register Endpoint6 Control Register Endpoint0 Control and Status Register Endpoint1 Control and Status Register Endpoint2 Control and Status Register Endpoint3 Control and Status Register Endpoint4 Control and Status Register Endpoint5 Control and Status Register Endpoint6 Control and Status Register FIFO 0 Data Register FIFO 1 Data Register FIFO 2 Data Register FIFO 3 Data Register FIFO 4 Data Register FIFO 5 Data Register FIFO 6 Data Register Byte Count FIFO 0 Register [7:0] Byte Count FIFO 1 Register [7:0]
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Table 14. USB Register Set (Continued)
Register FBYTE_CNT2_L FBYTE_CNT3_L FBYTE_CNT4_L FBYTE_CNT5_L FBYTE_CNT6_L FBYTE_CNT0_H FBYTE_CNT1_H FBYTE_CNT2_H FBYTE_CNT3_H FBYTE_CNT4_H FBYTE_CNT5_H FBYTE_CNT6_H USB_SLP_EN USB_IRQ_EN USB_IRQ_STAT USB_BUS_STAT PA_EN USB_DMA_ADL USB_DMA_ADH USB_DMA_PLR USB_DMA_EAD USB_DMA_TPL USB_DMA_EN Address 0x0BD 0x0BC 0x0BB 0x0BA 0x0B9 0x0AF 0x0AE 0x0AD 0x0AC 0x0AB 0x0AA 0x0A9 0x100 0x101 0x102 0x103 0x104 0x105 0x106 0x107 0x108 0x109 0x10a Default 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 Function Byte Count FIFO 2 Register [7:0] Byte Count FIFO 3 Register [7:0] Byte Count FIFO 4 Register [7:0] Byte Count FIFO 5 Register [7:0] Byte Count FIFO 6 Register [7:0] Byte Count FIFO 0 Register [10:8] Byte Count FIFO 1 Register [10:8] Byte Count FIFO 2 Register [10:8] Byte Count FIFO 3 Register [10:8] Byte Count FIFO 4 Register [10:8] Byte Count FIFO 5 Register [10:8] Byte Count FIFO 6 Register [10:8] Sleep Mode Control Master Interrupt Enable Master Interrupt Status USB Bus Reset Condition Pair Addressing Enable DMA Address LO DMA Address HI DMA Packet Length Requested DMA Target Endpoint Address DMA Transferred Packet Length DMA Enable
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USB_DMA_EN: Enable Register for the Tx or Rx DMA between the DPRMA and the USB
Register Address: Default State:
Bit 7-2 1 0 Field Reserved USB_RDMA_EN USB_TDMA_EN W/R W/R
0x10A 0x00
AVR Description Reserved and set to 0 Enables Receive DMA (for OUT EPs). This bit is automatically cleared after the end of the DMA. Enables Transmit DMA (for IN EPs). This bit is automatically cleared after the end of the DMA.
USB_DMA_TPL: USB DMA Transferred Packet Length.
Register Address: Default State:
Bit 7-0 Field TPL[7:0]
0x109 0x00
AVR R Description Returns the number of bytes transferred during the last DMA
USB_DMA_EAD: USB DMA Endpoint.
Register Address: Default State:
Bit 7-0 Field FDRA[7:0]
0x108 0x00
AVR W/R Description The AVR writes the offset byte of FDRx address, depending on the Endpoint that is going to send or has received data: The following Endpoints with the corresponding offset bytes are supported by the DMA channels: FDR1- 0xCE FDR2- 0xCD FDR3- 0xCC FDR4- 0xCB FDR5- 0xCA FDR6- 0xC9
USB_DMA_PLR: USB DMA Packet Length Register
Register Address: Default State:
Bit 7-0 Field PLR[7:0]
0x107 0x00
AVR W/R Description The AVR writes the number of bytes for the DMA that follows.
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1643C-USB-10/02
USB_DMA_ADH: USB DMA DPRAM Address High order bits
Register Address: Default State:
Bit 7-3 2-0 Field Reserved UDA[10:8] W/R These three bits along with the eight bits of the USB_DMA_ADL forms the target address at the DPRAM that the DMA channel will use
0x106 0x00
AVR Description
USB_DMA_ADL: USB DMA DPRAM Address Low order byte
Register Address: Default State:
Bit 7-0 Note: Field UDA[7:0]
0x105 0x00
AVR W/R Description The least significant byte of the target address at the DPRAM that the DMA channel will use(1)
1. The 10 bit value formed by the previous two registers point at any location into the DPRAM from 0 to 2048. In order to access the same position from the AVR, the Base Address of the DPRAM (0x3000) should be added to the above location
PA_EN: USB Pair Addressing Enable
Register Address: Default State:
Bit 7-4 3-1 Field Reserved UPA[3:1] W/R The Endpoints EP1-EP6 use the USB physical addresses 1-7 respectively. By setting any of the these bits a pair of EPs, consisting of one IN and one OUT EP, is formed as follows: UPA[1]: EP4 has the same USB Physical address with EP1 UPA[2]: EP5 has the same USB Physical Address with EP2 UPA[3]: EP6 has the same USB Physical Address with EP3
0x104 0x00
AVR Description
USB_BUS_STAT: USB Bus State
Register Address: Default State:
Bit 7-4, 2-0 3 Field Reserved USB_BUS_RES R This bit is set when the USB bus is in reset state
0x103 0x00
AVR Description
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USB_IRQ_STAT: USB IRQ Status bits
Register Address: Default State:
Bit 7, 5-0 6 Field Reserved USB_EP_IRQ R/W This bit is set when an interrupt from the EPs 6-0 is produced. The register is cleared by writing 0x0
0x102 0x00
AVR Description
USB_IRQ_EN: USB IRQ Enable bits
Register Address: Default State:
Bit 7 6 Field USB_RES_IEN USB_GINT_EN
0x101 0x00
AVR W/R W/R Description When this bit is set, it enables the interrupt due to a USB Bus Reset condition USB Global Interrupt Enable: When this bit is set, enables the interrupts for the all USB EPs provided that the corresponding bits of the UIER register have been set.
5-0
Reserved
USB_SLP_EN: USB Sleep mode Enable
Register Address: Default State:
Bit 7-6, 40 5 Field Reserved USB_SLP_MOD W/R This bit is set to put the device into sleep mode when a Suspend condition is detected
0x100 0x00
AVR Description
FRM_NUM_H: Frame Number High Register
Register Address: Default State:
Bit 7-3 2-0 Field Reserved FCH[10:8] R
0x0FD 0x00
AVR Description Reserved and set to 0 These are the upper 3 bits of the 11-bit frame number of SOF packet.
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1643C-USB-10/02
FRM_NUM_L: Frame Number Low Register
Register Address: Default State:
Bit 7-0 Field FCL[7:0]
0x0FC 0x00
AVR R Description These are the lower 8 bits of the 11-bit frame number of SOF packet.
Global State Register
Register Address: Default State:
Bit 4-7 3 2 1 Field Reserved RSMINPR RMWUPE CONFG R W/R W/R
0x0FB 0000000000b
AVR Description Reserved Set by USB Hardware when a Resume is sent in the USB bus during remote wake-up feature (13 ms). Remote Wake-up Enable. This bit is set if the host enables the function's remote wake-up feature. Configured. This bit is set by the firmware after a valid SET_CONFIGURATION request is received. It is cleared by a reset or by a SET_CONFIGURATION with a value of 0. Function Address Enable. This bit is set by firmware after the status phase of a SET_ADDRESS request transaction. The host will use the new address, starting at the next transaction.
0
FADD Enable
W/R
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SPRSR: Suspend/Resume Register
Register Address: Default State:
Bit 7 6 5 4 3 2 Field Reserved Reserved Reserved Reserved SOF INT EXT RSM R R Start of Frame (SOF) Interrupt. A write on this bit clears the SOF interrupt Received External Resume. The USB Hardware sets this bit to denote an External Resume Interrupt. If RMWUPE = 1, a RESUME signal is sent in USB bus. Received Resume. The USB Hardware sets this bit when a USB resume signaling is detected at its port. Suspend. The USB Hardware sets this bit when it detects no SOF for 3 ms. The USB macro enters in SUSPEND mode, the processor has to go in SLEEP mode.
0x0FA xxxxx000b
AVR Description
1
RCVD RSM
R
0
SUSP
R
SPRSIE: Suspend/Resume Interrupt Enable Register
Register Address: Default State:
Bit 7 6 5 4 3 2 1 0 Field Reserved Reserved Reserved Reserved SOF IE EXTRSM IE RCVDRSM IE SUSP IE W/R W/R W/R W/R Enable SOF Interrupt Enable External Resume Signaling Interrupt: 1 = enable, 0 = disable Enable BUS Resume Signaling Interrupt: 1 = enable, 0 = disable Enable Suspend Signaling Interrupt: 1 = enable, 0 = disable
0x0F9 xxxxx000b
AVR Description
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1643C-USB-10/02
UISR - USB Interrupt Status Register
Register Address: Default State:
Bit 7 6 5 4 3 2 1 0 Field Reserved EP6 INT EP5 INT EP4 INT EP3 INT EP2 INT EP1 INT EP0 INT R/ R R R R R/ R/\ Endpoint 6Interrupt Endpoint 5 InterruptT Endpoint 4 Interrupt Endpoint 3 Interrupt Endpoint 2 Interrupt Endpoint 1 Interrupt Endpoint 0 Interrupt
0x0F7 0x00
AVR Description
The function interrupt bits will be set by the USB Hardware whenever the following bits in the corresponding endpoint's Control and Status registers are modified by the USB Hardware: 1. RX OUT Packet 2. TX Packet Ready 3. RX SETUP 4. TX Complete is set is set is set (Control and OUT endpoints) (Control endpoints only) (Control endpoints only) is cleared (Control and IN endpoints)
UIAR - USB Interrupt Acknowledge Register
The bits in this register are used to indirectly clear the bits of the UISR. A bit in the UISR is cleared if a "1" is written in the corresponding bit of UIAR. Register Address: Default State:
Bit 7 6 5 4 3 2 1 0 Field Reserved EP6 INTA EP5 INTA EP4 INTA EP3 INTA EP2 INTA EP1 INTA EP0 INTA W W W W W W W Endpoint 6 Interrupt Acknowledge Endpoint 5 Interrupt Acknowledge Endpoint 4 Interrupt Acknowledge Endpoint 3 Interrupt Acknowledge Endpoint 2 Interrupt Acknowledge Endpoint 1 Interrupt Acknowledge Endpoint 0 Interrupt Acknowledge
0x0F5 0x00
AVR Description
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UIER - USB Interrupt Enable Register
Register Address: Default State: 0x0F3 0x00
The bits in this register have the following meaning: 1 = enable interrupt 0 = disable interrupt
Bit 7 6 5 4 3 2 1 0 Field SOF IE EP6 IE EP5 IE EP4 IE EP3 IE EP2 IE EP1 IE EP0 IE AVR R/W R/W R/W R/W R/W R/W R/W R/W Description Enable SOF Interrupt Enable Endpoint 6 Interrupt Enable Endpoint 5 Interrupt Enable Endpoint 4 Interrupt Enable Endpoint 3 Interrupt Enable Endpoint 2 Interrupt Enable Endpoint 1 Interrupt Enable Endpoint 0 Interrupt
Function Address Register
The FIU contains an address register that contains the function address assigned by the host. This Function Address Register must be programmed by the processor once it has received a SET_ADDRESS command from the host and has completed the status phase of the transaction. After power up or reset, this register will contain the value of 0x00. The function enable bit (FEN) allows the firmware to enable or disable the function endpoints. The firmware will set this bit after receipt of a reset through the USB Hardware. Once this bit is set, the USB Hardware passes packets to and from the host. Register Address: Default State:
Bit 7 6-0 Field FEN FADD[6:0]
0x0F2 0x00
AVR W/R W/R Description Function Enable Function Address
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1643C-USB-10/02
ENDPPGPG: Endpoint Ping-pong Enable Register
Register Address: Default State:
Bit 7 6 5 4 3 2 1 0 Field Reserved PG PG 6 EN PG PG 5 EN PG PG 4 EN PG PG 3 EN PG PG 2 EN PG PG 1 EN PG PG 0 EN W W W W W W W Enable Endpoint 6 Ping-pong Enable Endpoint 5 Ping-pong Enable Endpoint 4 Ping-pong Enable Endpoint 3 Ping-pong Enable Endpoint 2 Ping-pong Enable Endpoint 1 Ping-pong Enable Endpoint 0 Ping-pong
0x0F2 0x00
AVR Description
Endpoint Control Register
Register Address: 0x0EF, ENDP0_CNTR Endpoint0 0x0EE, ENDP1_CNTR Endpoint1 0x0ED, ENDP2_CNTR Endpoint2 0x0EC, ENDP3_CNTR Endpoint3 0x0EB, ENDP4_CNTR Endpoint4 0x0EA, ENDP5_CNTR Endpoint5 0x0E9, ENDP6_CNTR Endpoint6 0x000000b
Field EPEDS Reserved Reserved DTGLE EPDIR Reserved and set to 0 R W/R Data Toggle. Identifies DATA0 or DATA1 packets. Endpoint Direction. Only applicable for non-control endpoints (0 = Out, 1 = In). Endpoint Type. These bits represent the type of the endpoint as follows: Bit1 Bit0 Type 00 Control 01 Isochronous 10 Bulk 11 Interrupt AVR W/R Description Endpoint Enable/Disable (0 = Disable Endpoint, 1 = Enable Endpoint) Reserved
Default State:
Bit 7 6 4-5 3 2
1-0
EPTYPE
W/R
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Endpoint Control and Status Register
Register Address: 0x0DF, FCSR0 Endpoint0 0x0DE, FCSR1 Endpoint1 0x0DD, FCSR2 Endpoint2 0x0DC, FCSR3 Endpoint3 0x0DB, FCSR4 Endpoint4 0x0DA, FCSR5 Endpoint5 0x0D9, FCSR6 Endpoint6 00000000b
AVR W/R Description Set by the processor to indicate to the USB Hardware the direction of a control transfer. 0 = control write (no data stage) 1 = control read This bit is used by control endpoints only. Indicate that the processor has placed the last data packet in FIFO0, or that the processor has processed the last data packet it expects from the host. Set by the processor to indicate a stalled endpoint. The USB Hardware will send a STALL handshake as a response to the next IN or OUT token. Indicates that the processor has loaded the FIFO with a packet of data. This bit is cleared by USB Hardware after the USB host acknowledges the packet. For ISO endpoints, this bit is cleared unconditionally after the data is sent. The USB Hardware sets this bit after a STALL is sent to the host. Indicates end of data stage for the control endpoint only. The USB Hardware sets this bit when it receives a valid setup packet from the host. This bit is used by control endpoints only. Indicates that the USB Hardware has decoded an OUT token and that the data is in the FIFO. The USB Hardware sets this bit to indicate to a control endpoint that it has received an ACK handshake from the host.
Default State:
Bit 7 Field Control Direction
6
Data End
W/R
5
Force Stall
W/R
4
TX Packet Ready
W/R
3
Stall Snd
R/C
2
RX SETUP
R/C
1 0
RX OUT Packet TX Complete
R/C W/R
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1643C-USB-10/02
* Control Direction This bit is used by control endpoints only and is used by firware to indicate the direction of a control transfer. It is written by the firware after it receives a RX SETUP Interrupt. The USB Hardware uses this bit to determine the status phase of a control transfer. * Data End This bit is used only by control endpoints together with bit 1 (TX Packet Ready) to signal the USB Hardware to go to the STATUS phase after the packet currently residing in the FIFO is transmitted. After the USB Hardware completes the STATUS phase, it will interrupt the processor without clearing this bit.
Caution:
Since the data end bit signals "END OF TRANSACTION", any other endpoint controller bit set after the DATA END is not considered by the ping-pong controller. That is why Tx_Packet Ready should be set before Data_End. * Force Stall The processor sets this bit if it wants to force a STALL if an unsupported request is received or if the host continues to ask for data after the data is exhausted. This bit should be set at the end of any data phase or setup phase. * Stall Snd The USB Hardware sets this bit after a STALL has been sent. The firmware uses this bit when responding to a USB GetStatus request. * TX Packet Ready This bit is used for the following operations: 1. Control read transactions by a control endpoint 2. IN transactions with DATA1 PID to complete the status phase for a control endpoint, when this bit is "0", but bit Data End (bit 4) is "1" 3. By a BULK IN or ISO IN or INT IN endpoint The processor should write into the FIFO only if this bit is cleared. After it has completed writing the data, it should set this bit. The data can be of zero length. For a control endpoint, the processor should write to the FIFO only while bit 6 (TX Packet Requested) is set. The USB Hardware clears this bit after it receives an ACK. If the interrupt is enabled, clearing this bit by the USB Hardware causes an interrupt to the processor. * RX SETUP This bit is used by control endpoints only to signal to the processor that the USB Hardware has received a valid SETUP packet and that the data portion of the packet is stored in the FIFO. The USB Hardware will clear all other bits in this register and will set RX SETUP. If the corresponding interrupt is enabled, the processor will be interrupted when RX SETUP is set. After the completion of reading the data from the FIFO, the firmware should clear this bit.
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* RX OUT Packet The USB Hardware sets this bit after it has stored the data of an OUT transaction in the FIFO. While this bit is set, the USB Hardware will NAK all OUT tokens. For control endpoints only, bit 7 of this register, Enable Control Write, has to be set for the USB Hardware to accept the OUT data. The USB Hardware will not overwrite the data in the FIFO except for an early USB setup request. Bit RX OUT Packet is used for the following operations: 1. Control write transactions by a control endpoint. 2. OUT transaction with DATA1 PID to complete the status phase of a control endpoint. 3. By a BULK OUT or ISO OUT or INT OUT endpoint. Setting this bit causes an interrupt to the processor if the interrupt is enabled. The firmware clears this bit after the FIFO are read. * TX Complete This bit is used by USB Hardware in a control endpoint to signal to the processor that it has successfully completed certain transactions. TX Complete is set at the completion of a: 1. Control read data stage 2. Status stage without data stage 3. Status stage after a control write transaction
FIFO Data Registers
These are dual function buffer registers. Received data are read by the processor from the endpoint's FIFO through these data registers. In the transmit mode, the processor writes to the FIFO through this register. Register Address: 0x0CF, FDR0 Function Endpoint0 0x0CE, FDR1 Function Endpoint1 0x0CD, FDR2 Function Endpoint2 0x0CC, FDR3 Function Endpoint3 0x0CB, FDR4 Function Endpoint4 0x0CA, FDR5 Function Endpoint5 0x0C9, FDR6 Function Endpoint6 00000000b
AVR W/R Description Data to be written to FIFO or data to be read from the FIFO
Default State:
Bit 7-0 Field FIFO DATA[7:0]
61
1643C-USB-10/02
* Byte Count Registers Each endpoint has a register that stores the number of bytes received by the USB Hardware. Register Address: 0x0BF, FBYTE_CNT0_L Endpoint0 0x0BE, FBYTE_CNT1_L Endpoint1 0x0BD, FBYTE_CNT2_L Endpoint2 0x0BC, FBYTE_CNT3_L Endpoint3 0x0BB, FBYTE_CNT4_L Endpoint4 0x0BA, FBYTE_CNT5_L Endpoint5 0x0B9, FBYTE_CNT6_L Endpoint6 0x0AF, FBYTE_CNT0_H Endpoint0 0x0AE, FBYTE_CNT1_H Endpoint1 0x0AD, FBYTE_CNT2_H Endpoint2 0x0AC, FBYTE_CNT3_H Endpoint3 0x0AB, FBYTE_CNT4_H Endpoin4 0x0AA, FBYTE_CNT5_H Endpoint5 0x0A9, FBYTE_CNT6_H Endpoint6 00000000b
Default State: FBYTE_CNT_L
Bit 7-0 Field BYTCT[7:0]
AVR R
Description Length of data packet in FIFO
FBYTE_CNT_H
Bit 7-3 2-0 2-0 Field Reserved BYTCT[10:8] ENDSZ[10:8] AVR Reserved R R Description Reserved Length of data packet in FIFO Endpoint Size [10:8]
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Electrical Characteristics
Absolute Maximum Ratings*
Operating Temperature......................................................TBD Storage Temperature .........................................................TBD Voltage on Any Pin with Respect to Ground ........................................ 3.0V to 3.6V Maximum Operating Voltage ............................................ 3.7V DC Output Current...................................................... 16.0 mA *NOTICE: Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
DC Characteristics
The values shown in this table are valid for TA = 0C to 85C, VCC = 3.3V unless otherwise noted.
Power Supply
Symbol VCC ICC ICCS Parameter Power Supply Supply Current Suspended Device Current Condition Min Max 3.3 50.0 200.0 Unit V mA A
USB Signals: DP, DM
Symbol ILO VDI VCM VSE VCRS VOL1 VOH1 Parameter High-Z Data Line Leakage Differential Input Sensitivity Differential Common Mode Range Single-ended Receiver Threshold Output Signal Crossover Static Output Low Static Output High Except first transition from idle state RL of 15 k to 3.6V RL of 15 k to GND Condition 0V < VIN < 3.3V DPx and DMx Min -10.0 0.2 0.8 0.8 1.3 2.5 2.0 2.0 0.3 Max +10.0 Unit A V V V V V
Oscillator Signals: OSC1, OSC2
Symbol VLH VHL CX1 CX2 C12 tSU Note: Parameter OSC1 Switching Level OSC1 Switching Level Input Capacitance, OSC1 Output Capacitance, OSC2 OSC1/2 Capacitance Start-up Time 6 MHz, fundamental
(1)
Condition
Min 0.47 0.67
Max 1.20 1.44 9.0 9.0 1.0 2.0
Unit V V pF pF pF ms
1. OSC2 must not be used to drive other circuitry.
63
1643C-USB-10/02
AC Characteristics
DP, DM Driver Characteristics
Symbol tR tF tRFM VCRS ZDRV Note:
(1)
Parameter Rise Time Fall Time tR/tF Matching Output Signal Crossover Driver Output Resistance
Condition CL = 50 pF CL = 50 pF
Min 4.0 4.0 90.0
Max 20.0 20.0 110.0 2.0 44.0
Unit ns ns % V W
Except first transition from idle state Steady-state drive
1.3 29.0
1. With external 27W series resistor.
DP, DM Data Source Timings
Symbol tDRATE tFRAME tDJ1 tDJ2 tFDEOP tFEOPT tFEOPR tJR1 tJR2 tFST Parameter Full-speed Data Rate Frame Interval Source Differential Driver Jitter to Next Transition for Paired Transitions Source Jitter for Differential Transition to SE0 Transition Source SE0 Interval of EOP Receiver SE0 Interval of EOP Receiver Data Jitter Tolerance to Next Transition for Paired Transitions Width of SE0 Interval during Differential Transition Condition Average Bit Rate Min 11.97 0.9995 -3.5 -4.0 -2.0 160.0 82.0 -18.5 -9.0 18.5 9.0 14.0 Max 12.03 1.0005 3.5 4.0 5.0 175.0 Unit Mbps ms ns ns ns ns ns ns ns ns
64
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(c) Atmel Corporation 2002. Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company's standard warranty which is detailed in Atmel's Terms and Conditions located on the Company's web site. The Company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel's products are not authorized for use as critical components in life support devices or systems. ATMEL (R), DataFlash (R) and AVR (R) are the registered trademarks of Atmel. Other terms and product names may be the trademarks of others. Printed on recycled paper.
1643C-USB-10/02 xM

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